Arsenic decapping and pre-atomic layer deposition trimethylaluminum passivation of Al2O3/InGaAs(100) interfaces

Ahn, Jaehwan; Kent, Tyler; Chagarov, Evgueni; Tang, Kechao; Kummel, Andrew C.; McIntyre, Paul C.

doi:10.1063/1.4818330

Cited by 45 publications

(41 citation statements)

References 25 publications

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“…Examples of p-and n-type C-V and G-V data are shown in Fig. 8 [13]. The dispersions in accumulation have been well explained by a one-band N bt model for majority carriers only [14].…”

Section: Correlations With Experimental Datamentioning

confidence: 72%

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A Unified Two-Band Model for Oxide Traps and Interface States in MOS Capacitors

Taur

Chen

Xie

et al. 2015

IEEE Trans. Electron Devices

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The distributed oxide trap model based on tunneling of carriers from the semiconductor surface is unified with the two-band Shockley-Read-Hall type of capture and emission model for interface states. The new model explains the often observed upturn of MOS conductance at high frequencies when biased in inversion. The unified two-band model fully covers both types of charge traps in all MOS bias regions. Index Terms-InGaAs, interface state model, MOS, oxide traps.

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“…Examples of p-and n-type C-V and G-V data are shown in Fig. 8 [13]. The dispersions in accumulation have been well explained by a one-band N bt model for majority carriers only [14].…”

Section: Correlations With Experimental Datamentioning

confidence: 72%

“…Letting Y n (x +δx) be Y n (x)+(dY n /dx)δx, etc. derives the three differential equations (11)- (13).…”

Section: Appendix a To Y And Y To Admittance Transformationsmentioning

confidence: 99%

A Unified Two-Band Model for Oxide Traps and Interface States in MOS Capacitors

Taur

Chen

Xie

et al. 2015

IEEE Trans. Electron Devices

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“…Several tens of nm of arsenic cap can protect the pristine GaAs layer from ambient oxidation, allowing the wafers to be transported in air. This tactic is well‐known in the III–V community well before oxide epitaxy has been considered . The samples can then be loaded into an oxide epitaxy system, where the arsenic cap can be desorbed at low temperatures of 300–400 °C, which is enough to desorb the amorphous As layer on the surface, but not enough to release it from the GaAs crystal.…”

Section: Growth Physical and Electronic Structurementioning

confidence: 99%

Epitaxial Oxides on Semiconductors: From Fundamentals to New Devices

Kumah

Ngai

Kornblum

2019

Adv Funct Materials

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Functional oxides are an untapped resource for futuristic devices and functionalities. These functionalities can range from high temperature superconductivity to multiferroicity and novel catalytic schemes. The most prominent route for transforming these ideas from a single device in the lab to practical technologies is by integration with semiconductors. Moreover, coupling oxides with semiconductors can herald new and unexpected functionalities that exist in neither of the individual materials. Therefore, oxide epitaxy on semiconductors provides a materials platform for novel device technologies. As oxides and semiconductors exhibit properties that are complementary to one another, epitaxial heterostructures comprised of the two are uniquely poised to deliver rich functionalities. This review discusses recent advancements in the growth of epitaxial oxides on semiconductors, and the electronic and physical structure of their interfaces. Leaning on these fundamentals and practicalities, the material behavior and functionality of semiconductor-oxide heterostructures is discussed, and their potential as device building blocks is highlighted. The culmination of this discussion is a review of recent advances in the development of prototype devices based on semiconductor-oxide heterostructures, in areas ranging from silicon photonics to photocatalysis. This overview is intended to stimulate ideas for new concepts of functional devices and lay the groundwork for their realization.

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“…38 Even though the lowest D it values reported in this study are 1-2 orders of magnitude greater than those typical of SiO 2 /Si interfaces, the obtained values are low for high-k/InGaAs gate stacks, which typically display D it values in the range of 1.0 × 10 12 cm −2 eV −1 to 1.0 × 10 13 cm −2 eV −1 . 16,39,40 In addition, there are several potential pitfalls in D it analysis of III-V MOS devices, requiring application of methods, such as the full interface state model used in this report, that avoid unphysical D it extraction and underestimation of the trap density 19 that may affect other results described in the literature. Finally, the interface defects densities observed for the studied HfO 2 /InGaAs gate stacks are well within the useful range for potential application in end-of-roadmap MOS devices.…”

Section: X-ray Photoelectron Spectroscopymentioning

confidence: 99%

The influence of surface preparation on low temperature HfO2 ALD on InGaAs (001) and (110) surfaces

Kent

Tang

Chobpattana

et al. 2015

The Journal of Chemical Physics

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Current logic devices rely on 3D architectures, such as the tri-gate field effect transistor (finFET), which utilize the (001) and (110) crystal faces simultaneously thus requiring passivation methods for the (110) face in order to ensure a pristine 3D surface prior to further processing. Scanning tunneling microscopy (STM), x-ray photoelectron spectroscopy (XPS), and correlated electrical measurement on MOSCAPs were utilized to compare the effects of a previously developed in situ pre-atomic layer deposition (ALD) surface clean on the InGaAs (001) and (110) surfaces. Ex situ wet cleans are very effective on the (001) surface but not the (110) surface. Capacitance voltage indicated the (001) surface with no buffered oxide etch had a higher C(max) hypothesized to be a result of poor nucleation of HfO2 on the native oxide. An in situ pre-ALD surface clean employing both atomic H and trimethylaluminum (TMA) pre-pulsing, developed by Chobpattana et al. and Carter et al. for the (001) surface, was demonstrated to be effective on the (110) surface for producing low D(it) high C(ox) MOSCAPs. Including TMA in the pre-ALD surface clean resulted in reduction of the magnitude of the interface state capacitance. The XPS studies show the role of atomic H pre-pulsing is to remove both carbon and oxygen while STM shows the role of TMA pre-pulsing is to eliminate H induced etching. Devices fabricated at 120 °C and 300 °C were compared.

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Arsenic decapping and pre-atomic layer deposition trimethylaluminum passivation of Al2O3/InGaAs(100) interfaces

Cited by 45 publications

References 25 publications

A Unified Two-Band Model for Oxide Traps and Interface States in MOS Capacitors

A Unified Two-Band Model for Oxide Traps and Interface States in MOS Capacitors

Epitaxial Oxides on Semiconductors: From Fundamentals to New Devices

The influence of surface preparation on low temperature HfO2 ALD on InGaAs (001) and (110) surfaces

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