Artificial Neural Network-Based 4-D Hyper-Chaotic System on Field Programmable Gate Array

Abstract

In this presented study, a 4-D hyper-chaotic system newly proposed to the literature, has been implemented as Multi-Layer Feed-Forward Artificial Neural Network-based on FPGA chip with 32-bit IEEE-754-1985 floating-point number standard to be utilized in real time chaos-based applications. In the first step of the study, 4-D hyper-chaotic system has been numerically modeled on FPGA using Dormand-Prince numeric algorithm. In the second step, the data set (4X10,000) obtained from Matlab-based numeric model has been divided into two parts as training data set (4X8,000) and test data set (4X2,000) to create ANN-based 4-D hyper-chaotic system. A Multi-Layer Feed-Forward ANN structure with 4 inputs and 4 outputs has been constructed for ANN-based 4-D hyper-chaotic system. This structure has only one hidden layer and there are 8 neurons having Tangent Sigmoid activation function used as the activation function in each neuron. 2.58E-07 Mean Square Error (MSE) value has been obtained from the training of ANN-based 4-D hyper-chaotic system. In the third step, after the successful training of ANN-based 4-D hyper-chaotic system, the design of ANN-based 4-D hyper-chaotic system has been carried out on FPGA by taking the bias and weight values of the ANN structure as reference. In this step, at first, Matlab-based Feed-Forward Multi-Layer 4X8X4 network structure has been coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL) to be implemented on FPGA chips. Then, the bias and weight values of the ANN structure has been converted from decimal number system to floating-point number standard and these converted values have been embedded into the network structure. In the last step, the ANN-based 4-D hyper-chaotic system designed on FPGA has been synthesized and tested using Xilinx ISE Design Suite. The chip statistics have been given after the Place&Route process carried out for the Virtex XC6VHX255T-3FF1155 FPGA chip. The maximum operating frequency of ANN-based 4-D hyper-chaotic system on FPGA has been obtained as 240.861 MHZ.

Artificial intelligence techniques for encrypt images based on the chaotic system implemented on field-programmable gate array

“…The Matlab Neural Network Processing Toolbox was used for the offline training stage. Following the training phase, the appropriate network parameters (weights and biases) were determined and then deployed on the FPGA [9]. Throughout the design process, several architectural types were examined.…”

“…As a result, an acceptable value of MSE can be utilized for the implementation of the ANN-based CCS. An FPGA implementation not only provides the option of parallelism, but it also lowers design costs and increases flexibility, making it particularly suitable for ANN applications [9]. That is why an ANN-based CCS was built using FPGA.…”

The Proposition of Three Approaching Ways to Implement Tan-sigmoid Activation Function in FPGA

“…Tan-Sigmoid and Log -sigmoid activation functions are widely used in artificial neural networks. That which can be represented in equations ( 1) and (2) [18] [25] [22].…”

“…Cyclone IV E series board tested in FPGA Altera D2-115 [17]. Based on the neural network design, Koyuncu et al [18] presented the hydrogen energy system for running on VHDL Field programming gate chips with 32-bit floating-point IEEE-754-1985 and synthesized to use the programming tools of Xilinx ISE support the Virtx-7 FPGA chip (VC7VX485T, Package FFG 1761 2 speed) Program 14.7. (As usage is reduced number of registers for slices is 17%, the number of LUTs for Slice is 35%, the number of DSP48EL is 1%, the number for IOBs is 27%, and the high frequency of the clock 281.702 MHZ).…”

New artificial neural network design for Chua chaotic system prediction using FPGA hardware co-simulation

“…Numerous studies and research based on a prediction of chaotic systems using neural networks have been established such as: Alçın et al [4] implemented the Pehlivan-Uyaroglu chaotic system (PUCS) in very-high-density lipoprotein (VHDL) IEEE-754 32 bit floating-point standard by using artificial neural [7], in this research, a novel four-dimensional hyper-chaotic system was implemented as a multi-layer feedforward artificial neural network (FFANN) on an FPGA chip with a 32-bit IEEE-754-1985 floating-point number standard for use in real-time chaos-based applications. Zhang and Lei [8] examines the training efficiency of multilayer ANN architectures for chaotic systems implementation.…”