AS/400 64-bit powerPC-compatible processor implementation

Borkenhagen, John M.; Handlogten, Glen H.; Irish, John D.; Levenstein, S.

doi:10.1109/iccd.1994.331886

Cited by 6 publications

(5 citation statements)

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“…As a lightweight experimental environment, we employ a high-level software model of the two arithmetic pipes of the NorthStar superscalar in-order processor and the dispatch unit, also used in [5]. The NorthStar processor, also known as the RS64-II or PowerPC A50, was released by IBM in the late 1990s, featuring a RISC instruction set architecture [2]. The high-level software model consists of two main components.…”

Section: The Northstar Pipelinementioning

confidence: 99%

How To Catch A Lion In The Desert -- On The Solution Of The Coverage Directed Generation (CDG) Problem

Gal,

Haber,

Irwin

et al. 2019

Preprint

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The testing and verification of a complex hardware or software system, such as modern integrated circuits (ICs) found in everything from smartphones to servers, can be a difficult process. One of the most difficult and time-consuming tasks a verification team faces is reaching coverage closure, or hitting all events in the coverage space. Coverage-directed-generation (CDG), or the automatic generation of tests that can hit hard-to-hit coverage events, and thus provide coverage closure, holds the potential to save verification teams significant simulation resources and time. In this paper, we propose a new approach to the CDG problem by formulating the CDG problem as a noisy derivative free optimization (DFO) problem. However, this formulation is complicated by the fact that derivatives of the objective function are unavailable, and the objective function evaluations are corrupted by noise. We solve this noisy optimization problem by utilizing techniques from direct optimization coupled with a robust noise estimator, and by leveraging techniques from inverse problems to estimate the gradient of the noisy objective function. We demonstrate the efficiency and reliability of this new approach through numerical experiments with an abstract model of part of IBM's NorthStar processor, a superscalar in-order processor designed for servers.

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Section: The Northstar Pipelinementioning

confidence: 99%

How To Catch A Lion In The Desert -- On The Solution Of The Coverage Directed Generation (CDG) Problem

Gal,

Haber,

Irwin

et al. 2019

Preprint

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“…There are several other contemporary processor designs that are specifically focused on commercial markets [5,23]. 7 Several papers from Stanford have advocated and evaluated the use of chip multiprocessing (CMP) in the context of workloads such as SPEC [15,29,33], and the Hydra project is exploring CMP with a focus on thread-level speculation [16,17].…”

Section: Discussion and Related Workmentioning

confidence: 99%

“…Piranha supports a number of elementary Reliability, Availability, and Serviceability (RAS) features such as redundancy on all memory components, CRC protection on most datapaths, redundant datapaths, protocol error recovery 5 , error logging, hotswappable links, and in-band system reconfiguration support. Furthermore, Piranha attempts to provide a platform for investigating advanced RAS features for future large-scale servers.…”

Section: Reliability Featuresmentioning

confidence: 99%

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Piranha: a scalable architecture based on single-chip multiprocessing

Barroso¹,

Gharachorloo²,

McNamara³

et al.

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201)

184

281

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The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instructionlevel parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors targeted at commercial servers. This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multiprocessing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.

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“…The IBM RS/6000 S80 is a shared-memory symmetric multiprocessor based on the PowerPC RS64-III (Pulsar) microprocessor [5,25]. Pulsar is a four-issue in-order superscalar processor with a five stage RISC pipeline.…”

Section: Methodsmentioning

confidence: 99%