ASAM: Automatic architecture synthesis and application mapping

Jóźwiak, L.; Lindwer, Menno; Corvino, Rosilde; Meloni, Paolo; Micconi, Laura; Madsen, Jan; Diken, Erkan; Gangadharan, Deepak; Jordans, Roel; Pomata, Sebastiano; Pop, Paul; Tuveri, Giuseppe; Raffo, Luigi; Notarangelo, Giuseppe

doi:10.1016/j.micpro.2013.08.006

Cited by 23 publications

(5 citation statements)

References 36 publications

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“…The slight differences cannot be considered a limiting factor for the exploitation of the architecture in real-time closed-loop experiments, since the global firing patterns are respected. Even though the proposed architecture is not highly optimized, because of the need to ensure flexibility at this development stage, it is possible to pursue energy/performance efficiency by means of fine application-driven customization of the hardware architecture, that requires adequate support by advanced design tools (Jozwiak et al, 2012 , 2013 ). The proposed approach can evolve in such a direction for closed-loop implantable implementations.…”

Section: Discussionmentioning

confidence: 99%

An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks

et al. 2017

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In the last years, the idea to dynamically interface biological neurons with artificial ones has become more and more urgent. The reason is essentially due to the design of innovative neuroprostheses where biological cell assemblies of the brain can be substituted by artificial ones. For closed-loop experiments with biological neuronal networks interfaced with in silico modeled networks, several technological challenges need to be faced, from the low-level interfacing between the living tissue and the computational model to the implementation of the latter in a suitable form for real-time processing. Field programmable gate arrays (FPGAs) can improve flexibility when simple neuronal models are required, obtaining good accuracy, real-time performance, and the possibility to create a hybrid system without any custom hardware, just programming the hardware to achieve the required functionality. In this paper, this possibility is explored presenting a modular and efficient FPGA design of an in silico spiking neural network exploiting the Izhikevich model. The proposed system, prototypically implemented on a Xilinx Virtex 6 device, is able to simulate a fully connected network counting up to 1,440 neurons, in real-time, at a sampling rate of 10 kHz, which is reasonable for small to medium scale extra-cellular closed-loop experiments.

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Section: Discussionmentioning

confidence: 99%

An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks

et al. 2017

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“…There are several works in the field of automatic development of ASIPs. In [8], the proposed approach concentrates on dominating the automatic synthesis and mapping of a given application to heterogeneous massively-parallel MPSoCs based on ASIPs. The technique is based on ASAM (Automatic Architecture Synthesis and Application Mapping).…”

Section: Related Workmentioning

confidence: 99%

“…In most applications, the ASIP technology requires performance and energy usage compared to those of hardwired ASICs [8]. Some challenges arise in this field when stringent and conflicting specifications demand highly-optimized hardware architectures, which requires the exploration of hardware solutions with different design characteristics.…”

Section: Introductionmentioning

confidence: 99%

ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications

et al. 2023

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The adoption of customized ASIPs (Application Specific Instruction Set Processors) in embedded circuits is an important alternative for optimizing power consumption, silicon area, or processing performance according to the design requirements. The processor is implemented specifically for the target application, which allows the hardware customization in terms of instruction set architecture, data word length, memory size, and parallelism. This work describes an EDA tool for the semi-automatic development of ASIPs named ASIPAMPIUM. The strategy is to provide a set of integrated tools to interpret and generate a customized hardware for a given target application, including compilation, simulation, and hardware synthesis. From the C code description of the application, the tool returns a synthesizable hardware description of the processor. The proposed methodology is based on the adaptation of a new customizable microprocessor called PAMPIUM, which can be optimized in terms of silicon area, power consumption, or processing performance according to the target application. The ASIPAMPIUM tool provides a series of simulated data to the designer in order to identify optimization strategies in both software and hardware domains. We show the results for the implementation of an FFT algorithm using the proposed methodology, which achieved best results in terms of silicon area and energy consumption compared to other works described in the literature for both FPGA and silicon implementation. Moreover, measurement results of the implementation in silicon of a dedicated ASIP for interfacing with six sensors in real-time, including three I2C, an SPI, and an RS-232 interfaces, demonstrate the complete design flow, from the C code program to physical implementation and characterization. Aside from providing a short design time, the ASIPAMPIUM tool also affords a simple and intuitive design flow, allowing the designer to deal with different design trade-offs and objectives.

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“…Similar templates, exposing in general the same optimization knobs to the designer, can be constructed using different industrial and academic solutions available for the community, such as [26][27][28][29][30] . All these toolsets can generate simulation models, HDL description for implementation, and provide a re-targetable compiler that adapts compilation to the selected processor and system configuration.…”

Section: Macro-architectural Templatementioning

confidence: 99%