ASC: a stream compiler for computing with FPGAs

Abstract

Abstract-A stream compiler (ASC) for computing with field programmable gate arrays (FPGAs) emerges from the ambition to bridge the hardware-design productivity gap where the number of available transistors grows more rapidly than the productivity of very large scale integration (VLSI) and FPGA computer-aideddesign (CAD) tools. ASC addresses this problem with a softwarelike programming interface to hardware design (FPGAs) while keeping the performance of hand-designed circuits at the same time. ASC improves productivity by letting the programmer optimize the implementation on the algorithm level, the architecture level, the arithmetic level, and the gate level, all within the same C++ program.The increased productivity of ASC is applied to the hardware acceleration of a wide range of applications. Traditionally, hardware accelerators are tediously handcrafted to achieve top performance. ASC simplifies design-space exploration of hardware accelerators by transforming the hardware-design task into a software-design process, using only "GNU compiler collection (GCC)" and "make" to obtain a hardware netlist. From experience, the hardware-design productivity and ease of use are close to pure software development.This

Families of FPGA-based accelerators for approximate string matching

“…In order to make our result widely applicable, we base it on the semantics of the standardized synthesizable subset of a standardized hardware description language, VHDL [27]. That choice precludes use of non-standard OO vehicles, such as stream-oriented ASC [28], or one of the many research systems. It also precludes use of standardized OO hardware languages such as SystemC [29] and SystemVerilog [30], for which no standard synthesizable subset currently exists and for which vendor support varies widely.…”

Optimal implementation of combinational logic on look-up tables

“…The process is continued until a feasible circuit implementing the given function is found. Once a circuit is found, we automatically generate the hardware description in ASC [17], explicitly specifying the LUT configurations and interconnections to be mapped onto an actual FPGA. Additionally, for each circuit, we automatically generate a testbench, and simulate for the set of inputs specified in the truth table, comparing the result with the expected output.…”

High-Level Synthesis for FPGAs: From Prototyping to Deployment

“…FPGAs have continually improved in capacity and speed in recent years, and their programmability makes them an attractive platform for many applications in signal processing, communication, and HPC. There has been a strong desire to make FPGA programming easier, and many HLS tools are designed to specifically target FPGAs, including ASC [65], CASH [9], C2H [99], DIME-C [114], GAUT [23], Handel-C Compiler (now part of Mentor Graphics DK Design Suite) [96], Impulse C [75], ROCCC [88], [40], SPARK [41], [42], Streams-C [37], and Trident [83], [84]. ASIC tools also commonly provide support for targeting an FPGA tool flow in order to enable system emulation.…”