ASIP design methodologies: survey and issues

Jain, Manoj; Balakrishnan, M.; Kumar, Anshul

doi:10.1109/icvd.2001.902643

Cited by 81 publications

(37 citation statements)

References 18 publications

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“…De Gloria et al [DGF90] defines some main requirements for the design of an ASA, and in [JBK01], five general steps in ASIP synthesis are presented. Different design flows for ASIP design exists, such as the methodology presented in [Kuc99], and the ASSIST methodology [KJBK04].…”

Section: The Goal Of Asip Designmentioning

confidence: 99%

Ultra low power application specific instruction-set processor design for a cardiac beat detector algorithm

et al. 2009

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Focus: Computer architecture/arithmetic, Processor design, Continuous wavelet transform (CWT)IMEC-NL researches and develops wireless autonomous transducer solutions for Wireless Sensor Nodes (WSN) of which each component (radio, digital signal processors (DSPs), sensors, and actuators) is tailored to meet the tight power and performance constraints. The DSPs developed at IMEC-NL process the sensor node data locally, hence reducing power costly wireless data communication in order to minimize energy dissipation of the entire WSN. For this reason, the DSPs must be designed to run a specific application as efficient as possible.The assignment targets the design of an ASIP with Target processor design tools, and the research and mapping of a biomedical application on this processor. This task includes conversion of Matlab and/or generic C-code to platform related code, mapping it on a generic DSP, and retarget the DSP for the biomedical application. AbstractHigh efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption.By optimizing the processor for the application, or a set of applications, one could improve the computing power by introducing special purpose hardware units. The execution cycle count of the application would in this case be reduced significantly, and the resulting processor would consume less power.In this thesis, some research is done in how to optimize a software and hardware development for ultra low power consumption. A cardiac beat detector algorithm is implemented in ANSI C, and optimized for low power consumption, by using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies. This processor is optimized further for ultra low power consumption by applying application specific hardware, and by using several hardware power optimization techniques.A general processor and the optimized processor has been mapped on a chip, using a 90 nm low power TSMC process. Information about power dissipation is extracted through netlist simulation, and the results of both processors have been compared. The optimized processor consume 55% less average power, and the duty cycle of the processor, i.e., the time in which the processor executes its task with respect to the time budget available, has been reduced from 14% to 2.8%. The reduction in the total execution cycle count is 81%.The possibilities of applying power gating, or voltage and frequency scaling are discussed, and it is concluded that further reduction in power consumption is possible by applying these power optimization techniques. For a given case, the average leakage power dissipation is estimated to be reduced by 97.2%. v PrefaceDuring the work in this project, I got the opportunity to work with IMEC-NL, where I met very talented engineers and researchers. They gave me the freedom to use s...

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Section: The Goal Of Asip Designmentioning

confidence: 99%

Ultra low power application specific instruction-set processor design for a cardiac beat detector algorithm

et al. 2009

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“…Jain et al surveyed the state of art in ASIP design methodologies, and identified five key steps as application analysis, design space exploration, instruction set generation, software tool set generation and hardware synthesis [1][2][3]. According to this survey a typical approach is shown if Figure 1.…”

Section: Related Workmentioning

confidence: 99%

ADA: Applications Define ASIP

Jain¹

2014

IJCA

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Interest in Application Specific Instruction set Processors or ASIPs has increased significantly. Sincere efforts have been put in improving ASIP design methodologies in industry as well as in academia. By the close observation and analysis of these approaches, it was found that though the existing approaches are focusing on making the process automatic and providing better GUI to help the designers, core technique used in deciding the suitable architecture (processor and memory) is based on design space exploration. This exploration is done with the help of estimators. Such estimators are either simulator based or scheduler based. This study identifies that both types of techniques are very far from the ideal dream technique in which applications should have defined the suitable architecture configuration and these techniques are becoming unsuitable in current scenario. Each problem has a solution hidden in it. This scenario motivated us to propose a novel and revolutionary ASIP design technique making the dream true. The Proposed technique does not focuses on design space exploration, it focuses on directly defining processors for given applications rather than searching for suitable configuration in a jungle of configurations can be suggested by the architecture design space. General TermsComputer Architecture, Processor Design, Processor Design Technology.

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“…Code generation for embedded processors, micro-controllers and ASIPs is a mature domain of research and innovation, with branches and challenges in many technical areas [17,12].…”

Section: Related and Future Workmentioning

confidence: 99%

Code generation for an application-specific VLIW processor with clustered, addressable register files

Llopard

Cohen

Fabre

et al. 2013

Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems

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Modern compilers integrate recent advances in compiler construction, intermediate representations, algorithms and programming language front-ends. Yet code generation for application-specific architectures benefits only marginally from this trend, as most of the effort is oriented towards popular general-purpose architectures. Historically, non-orthogonal architectures have relied on custom compiler technologies, some retargettable, but largely decoupled from the evolution of mainstream tool flows.Very Long Instruction Word (VLIW) architectures have introduced a variety of interesting problems such as clusterization, packetization or bundling, instruction scheduling for exposed pipelines, long delay slots, software pipelining, etc. These have been addressed in the literature, with a focus on the exploitation of Instruction Level Parallelism (ILP). While these are well known solutions already embedded into existing compilers, they rely on common hardware functionalities that are expected to be present in a fairly large subset of VLIW architectures.This paper presents our work on back-end compiler for Mephisto, a high performance low-power application-specific processor, based on LLVM. Mephisto is specialized enough to challenge established code generation solutions for VLIW and DSP processors, calling for an innovative compilation flow. Conversely, even though Mephisto might be seen a somewhat exotic processor, its hardware characteristics such as addressable register files benefit from existing analyses and transformations in LLVM. We describe our model of the Mephisto architecture, the difficulties we encountered, and the associated compilation methods, some of them new and specific to Mephisto.

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ASIP design methodologies: survey and issues

Cited by 81 publications

References 18 publications

Ultra low power application specific instruction-set processor design for a cardiac beat detector algorithm

Ultra low power application specific instruction-set processor design for a cardiac beat detector algorithm

ADA: Applications Define ASIP

Code generation for an application-specific VLIW processor with clustered, addressable register files

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