Assembly process development of 50um fine pitch wire bonded devices

Yao, Yasuhiro; Xiong, Z.P.; Gu, Xin; Chua, K.H.; Lin, T.Y.

doi:10.1109/ectc.2004.1319366

Cited by 4 publications

(2 citation statements)

References 4 publications

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“…The pad damage can result in more ball bond lifts in ultra‐fine pitch wire bonding. A study of bonding using ϕ 0.9 mil wire reveals that the acceptable ratio of probe‐mark area over ball bond area is 20 per cent and the probe depth is 0.6 μ m. If the ratio is >20 per cent, ball lift can be observed after destructive wire pull testing (Yao et al , 2004).…”

Section: Challenges In Fine and Ultra‐fine Pitch Wire Bondingmentioning

confidence: 99%

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Fine and ultra‐fine pitch wire bonding: challenges and solutions

Zhong

2009

Microelectronics International

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PurposeThe purpose of this paper is to review recent advances in fine and ultra‐fine pitch wire bonding.Design/methodology/approachDozens of journal and conference articles published recently are reviewed.FindingsThe problems/challenges such as possible wire sweep and decreased bonding strength due to small wire sizes, non‐sticking, metal pad peeling, narrow process windows, wire open and short tail defects are analysed. The solutions to the problems and recent findings/developments in fine and ultra‐fine pitch wire bonding are discussed.Research limitations/implicationsBecause of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.Originality/valueThis paper attempts to provide an introduction to recent developments and the trends in fine and ultra‐fine pitch wire bonding. With the references provided, readers may explore more deeply by reading the original articles.

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Section: Challenges In Fine and Ultra‐fine Pitch Wire Bondingmentioning

confidence: 99%

“…Because most of bond pads were rectangular, the elliptical ball bond could increase the bonding area by 17‐20 per cent, and decrease the ratio of probe‐mark area over ball bond area. Thus, this method can reduce the effects of damaged probe marks (Yao et al , 2004).…”

Section: Solutions and Findings For Reliable Fine And Ultra‐fine Pitch Wire Bondingmentioning

confidence: 99%

Fine and ultra‐fine pitch wire bonding: challenges and solutions

Zhong

2009

Microelectronics International

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3D silicon integration

Knickerbocker

Andry

Dang

et al. 2008

2008 58th Electronic Components and Technology Conference

194

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BGA assembly process development for 45nm ELK CUP devices

Tseng¹,

Lin²,

Huang³

et al. 2008

2008 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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The object of this study is to develop a set of optimized assembly process parameters for BGA package using 45nm ELK (extreme Low-K) and CUP (circuit under pad) wafer which is driven by high speed and high I/O requested. Due to chip size shrinkage with electrical performance improvement, most of 0.13μm and 90nm wafer process technology are moving toward 65nm and even 45nm now. The ELK dielectric material for Inter-Level Dielectric (ILD) with the CUP has been designed to get more space for active circuit layout. But the poor mechanical properties of the low-k dielectric and the CUP structure circuit pad design make packaging assembly more challenges. The impacts of IC packaging assembly processes are including the wafer sawing, wire bonding, and molding process. For mass production purpose, the most effective parameters for 45nm ELK CUP wafer have been studied such as sawing blade type, sawing speed and sawing feeding rate for different wafer thickness, the wire bond time, bond power and bond force. To solve bond wire sweep and mold void issues, the properties of different molding compounds have been studied and assembly process parameters have been optimized. In the end, a real functional die of 45nm ELK with CUP design has been assembled into package level for reliability test using optimized process parameters. IntroductionIn the last decade, the electronics devices are requested to be smaller size, lighter weight, faster speed and lower cost. In the mean while, the I/O numbers increases for more functionality. Therefore, the wafer process technology is moving fast from 0.18um, 0.15um and 0.13um Aluminum standard wafer down to 90nm and 65nm Copper Low-K wafer for fast speed applications and more dice per wafer. Recently, the 45nm ELK wafer process technology is introduced and completely developed. The copper is used for inner layer circuits to replace Aluminum metal and the lower dielectric material (ELK) is used for inter-Level dielectric (ILD) to reduce RC circuit delay [1]. As wafer technologies shrinking rapidly faster than the size of wire bond pad, it becomes that bond pad occupy the circuit layout area in a silicon chip. If the active circuit of a chip can be placed under bond pads, the die cost could be reduced obviously and the design flexibility would also be improved. For those reasons, the ELK wafers [2] with circuit under pad (CUP) design are getting more and more popular. [3]

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Assembly process development of 50um fine pitch wire bonded devices

Cited by 4 publications

References 4 publications

Fine and ultra‐fine pitch wire bonding: challenges and solutions

Fine and ultra‐fine pitch wire bonding: challenges and solutions

3D silicon integration

BGA assembly process development for 45nm ELK CUP devices

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