Copper (Cu) bond wires are increasingly used in semiconductor components to replace gold (Au) bond wires, and applications for these components are expanding from consumer to high-reliability electronic systems. To assess the impact of this conversion on the overall component reliability, extended reliability testing beyond the typical JEDEC component qualification testing is needed. Additionally, key packaging materials such as molding compound also need to be re-evaluated as they may interact with Cu wire bond differently from Au wires and introduce new failure mechanisms. In this work, we investigate the impact of molding compound chemistry on the reliability performance by varying two material properties, pH level and Clconcentration. A total of 9 formulations are generated for a 16-lead SOP (Small Outline Package) package. The assembled components are subject to two acceleration tests including biased-HAST (Highly Accelerated Stress Testing) and HTS (High Temperature Storage) test. As a control, Au wires are used for some of the cells and are subject to the same acceleration tests as the Cu wire components. The failure rates for all of the experimental cells will be reported. The effects of pH and Cl-levels on the failure rates will be discussed. Additionally, analytical results on the failed components using FIB (Focus Ion Beam), SEM (Scanning Electron Microscopy), and EDX (Energy Dispersive X-ray) will be reported. The reliability testing and analytical results will demonstrate the importance of controlling molding compounds properties and provide guidelines for the selection of these materials. For high-reliability and mission-critical electronic systems, improved and better-controlled packaging material formulations will be needed to ensure the long-term reliability of components using Cu bond wires.

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The advanced Quad Flat No-Lead (aQFN) package is an enhanced version of conventional QFN with multiple row terminals of featuring higher number of I/O ports. The aQFN thermal and electrical performance are superior due to smaller profile and shorter interconnects and the solder wettability control and board-level thermo-mechanical reliability are greatly enhanced over conventional QFN because of the higher package standoff. aQFN provides similar I/O number approaching that of a BGA-type chip-scale package (FBGA) but much less cost since the expensive substrate is replaced by lead frame. aQFN turns out to be an ideal low cost solution for electrical components of portable telecommunication applications such as IrDA, blue-tooth, RFID, cell phone baseband etc. for its superior thermal, electrical, reliability performances and miniaturized package size, With such advantages, the replacement of FBGA with aQFN in low up to medium lead-count applications is therefore highly expectable, especially for handheld & PDA devices with its related applications. With such higher pin-count, multi-row and small terminal pitch than QFN, how to design the aQFN package terminals for printed circuit board layout and the stencil patterning and opening for solder paste printing become crucial issues. aQFN will be introduced in terms of its application advantages, development, fabrication process flow, SMT process with stencil design guideline for surface mount assembly yield. Finally, "Surface Mount Application Notes" have been issued.

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