Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

Abstract

Most of past evaluations of fat-trees for on-chip interconnection networks rely on oversimplifying or even irrealistic architecture and traffic pattern assumptions, and very few layout analyses are available to relieve practical feasibility concerns in nanoscale technologies. This work aims at providing an in-depth assessment of physical synthesis efficiency of fat-trees and at extrapolating siliconaware performance figures to back-annotate in the system-level performance analysis. A 2D mesh is used as a reference architecture for comparison, and a 65 nm technology is targeted by our study. Finally, in an attempt to mitigate the implementation cost of k-ary n-tree topologies, we also review an alternative unidirectional multi-stage interconnection network which is able to simplify the fat-tree architecture and to minimally impact performance.

Floorplan-Aware High Performance NoC Design

“…This proposal is based on the implementation of a decoupled fully buffered crossbar that enables scalable performance with the number of ports. This work, however, is not directly suitable for an onchip network scenario, where technology constraints impose new limitations, specially on the maximum operating frequency of the design [25].…”

“…Fat-trees are indirect topologies based on complete trees. In [25], the authors show how technology constraints impose severe limitations to the practical utilization of tree-based high-radix topologies. In [24], the authors go beyond the previous simplification, and reduce the fat-tree complexity by forcing a deterministic routing algorithm, developing the Reduced Unified Fat-Tree (RUFT).…”

“…Finally, tree-based networks are feasible if some simplifications are made [24,25], creating a fat-tree topology. A fat-tree topology (see Figure 2.9) is an indirect topology where the bandwidth is doubled at each upper layer, achieving full bisection bandwidth.…”

“…In this sense, researchers have developed more complex topologies that overcome the inefficiencies of basic ones but still being implemented as a planar structure. A flattened butterfly topology [21,22] (see Figure 1.4(b)), multi-stage networks such as the Clos network [23] (see Figure 1.4(d)), topologies based on fat-tree networks [24,25] (see Figure 1.4(e)), concentrated meshes (C-meshes) [26] (see Figure 1.4(a)), hierarchical topologies [27], or multidrop express channels (MEC) [28] (see Figure 1.4(c)) are some remarkable solutions recently suggested by researchers.…”

“…Networks as the fat-tree [70] or the multistage Clos network [67] are considered. In [25], Ludovici et al analyzed the feasibility of the on-chip fat-tree implementation. Fat-trees are indirect topologies based on complete trees.…”