Assessing the suitability of the NGMP multi-core processor in the space domain

Fernandez, Mikel; Gioiosa, Roberto; Quiñones, Eduardo; Fossati, L.; Zulianello, Marco; Cazorla, Francisco J.

doi:10.1145/2380356.2380389

Cited by 60 publications

(97 citation statements)

References 11 publications

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“…The high slowdown breaks the common wisdom that the expected slowdown due to contention would be up to 4x when consolidating in a multicore 4 tasks that fully utilize a shared resource each one in isolation. This is so because inappropriate design choices may lead to performance issues such as those related to short requests competing with long request, as already shown in some processors [9]. Thus, specific arbitration policies that fairly share bandwidth in terms of time rather than in terms of requests are needed.…”

Section: Background On Arbitration Policiesmentioning

confidence: 99%

Design and implementation of a fair credit-based bandwidth sharing scheme for buses

Slijepcevic

Hernández

Abella

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-Fair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case execution time (WCET) estimates in the context of critical real-time systems, for which performance guarantees are essential. Several hardware mechanisms exist for managing arbitration in those resources (buses, memory controllers, etc.). They typically attain fairness in terms of the number of slots each contender (e.g., core) gets granted access to the shared resource. However, those policies may lead to unfair bandwidth allocations for workloads with contenders issuing short requests and contenders issuing long requests. We propose a Credit-Based Arbitration (CBA) mechanism that achieves fairness in the cycles each core is granted access to the resource rather than in the number of granted slots. Furthermore, we implement CBA as part of a LEON3 4-core processor for the Space domain in an FPGA proving the feasibility and good performance characteristics of the design by comparing it against other arbitration schemes.

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Section: Background On Arbitration Policiesmentioning

confidence: 99%

Design and implementation of a fair credit-based bandwidth sharing scheme for buses

Slijepcevic

Hernández

Abella

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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“…Given a task set, T , in order to provide fully time-composable ETB C f T C i for each task, we employ a recent approach based on microbenchmarks, also known as resource stressing kernels (RSK) [29], [21], [13], [11]. RSK are specialized, single-phase user-level programs designed to stress each of the hardware shared resources in the processor.…”

Section: Deriving Etb Under Different Contention Conditionsmentioning

confidence: 99%

“…In [29], [13], the authors show that RSK produce greater contention interference on access to hardware shared resources than any real application or other benchmark that they could compare with. We therefore maintain that τ i 's fTC ETB can be determined when τ i runs in parallel with that RSK.…”

Section: Deriving Etb Under Different Contention Conditionsmentioning

confidence: 99%

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Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

Fernández

Abella

Quiñones

et al. 2015

2015 IEEE 18th International Symposium on Real-Time Distributed Computing

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Abstract-The timing verification of real-time singlecore systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes of the individual tasks, including the ETB, are studied from the system level perspective. The transition between those two steps involves accounting for the interference effects that arise when tasks contend for access to shared resource. The advent of multicore processors challenges the viability of this two-step approach because several complex contention effects at the processor level arise that cause tasks to be unable to make progress while actually holding the CPU, which are very difficult to tightly capture by simply inflating the tasks' ETB. In this paper we show how contention on access to hardware shared resources creates a circular dependence between the determination of tasks' ETB and their scheduling at run time. To help loosen this knot we present an approach that acknowledges different flavors of time composability, examining in detail the variant intended for partitioned scheduling, which we evaluate on two real processor boards used in the space domain.

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“…MC2 combines two techniques that have been classified as MBPTA compliant: software randomization [18] for cache-jitter management, and delay upperbounding for multicore contention management [16]. For the latter, since multicore contention can lead to very pessimistic WCET estimates [13] when contention bounds are provisioned for the worst possible contention, MC2 provides adaptable WCET estimates that depend on contenders' contention. Our results provides evidence that MC2 effectively captures the impact on execution time -and hence on WCET estimates -of both resources, and provides tight WCET estimates.…”

Section: Introductionmentioning

confidence: 99%

MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding

Diaz

Fernandez

Kosmidis

et al. 2017

Reliable Software Technologies – Ada-Europe 2017

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Abstract. In critical domains, reliable software execution is increasingly involving aspects related to the timing dimension. This is due to the advent of high-performance (complex) hardware, used to provide the rising levels of guaranteed performance needed in those domains. Caches and multicores are two of the hardware features that have the potential to significantly reduce WCET estimates, yet they pose new challenges on current-practice measurement-based timing analysis (MBTA) approaches. In this paper we propose MC2, a technique for multilevel-cache multicores that combines deterministic and probabilistic jitter-bounding approaches to reliably handle both the variability in execution time generated by caches and the contention in accessing shared hardware resources. We evaluate MC2 on a COTS quad-core LEON-based board and our initial results show how it effectively captures cache and multicore contention in pWCET estimates with respect to actual observed values.

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Assessing the suitability of the NGMP multi-core processor in the space domain

Cited by 60 publications

References 11 publications

Design and implementation of a fair credit-based bandwidth sharing scheme for buses

Design and implementation of a fair credit-based bandwidth sharing scheme for buses

Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding

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