Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

Fernández, Gabriel; Abella, Jaume; Quiñones, Eduardo; Fossati, L.; Zulianello, Marco; Vardanega, Tullio; Cazorla, Francisco J.

doi:10.1109/isorc.2015.43

Cited by 9 publications

(9 citation statements)

References 23 publications

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“…While our approaches focus on the application level, their work is more concerned with the safety of the underlying system. For example, they focus on improving the predictability and timing analysis of networks that connect individual microcontrollers inside cyber-physical systems [42][43][44], as well as timing issues related to the use of multicore microprocessors [45][46][47].…”

Section: Related Workmentioning

confidence: 99%

Automatic Code Generation of Safety Mechanisms in Model-Driven Development

Huning¹,

Pulvermueller²

2021

Electronics

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In order to meet regulatory standards in the domain of safety-critical systems, these systems have to include a set of safety mechanisms depending on the Safety Integrity Level (SIL). This article proposes an approach for how such safety mechanisms may be generated automatically via Model-Driven Development (MDD), thereby improving developer productivity and decreasing the number of bugs that occur during manual implementation. The approach provides a structured way to define safety requirements, which may be parsed automatically and are used for the generation of software-implemented safety mechanisms, as well as the initial configuration of hardware-implemented safety mechanisms. The approach for software-implemented safety mechanisms relies on the Unified Modeling Language (UML) for representing these mechanisms in the model and uses model transformations to realize them in an intermediate model, from which code may be generated with simple 1:1 mappings. The approach for hardware-implemented safety mechanisms builds upon a template-based code snippet repository and a graphical user interface for configuration. The approach is applied to the development of a safety-critical fire detection application and the runtime of the model transformations is evaluated, indicating a linear scalability of the transformation steps. Furthermore, we evaluate the runtime and memory overhead of the generated code.

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Section: Related Workmentioning

confidence: 99%

Automatic Code Generation of Safety Mechanisms in Model-Driven Development

Huning¹,

Pulvermueller²

2021

Electronics

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“…First, MDE allows the construction of complex software architectures, defining components with clear interfaces, thus facilitating the integration of new features through composability [9]. This design principle aims at ensuring that the nonfunctional requirements fulfilled when developing components in isolation are maintained at system integration, avoiding unpredictable and hidden behaviors.…”

Section: A Cpss Development: Model Driven Engineering (Mde)mentioning

confidence: 99%

The AMPERE Project: : A Model-driven development framework for highly Parallel and EneRgy-Efficient computation supporting multi-criteria optimization

Quiñones

Royuela

Scordino

et al. 2020

2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC)

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The high-performance requirements needed to implement the most advanced functionalities of current and future Cyber-Physical Systems (CPSs) are challenging the development processes of CPSs. On one side, CPSs rely on model-driven engineering (MDE) to satisfy the non-functional constraints and to ensure a smooth and safe integration of new features. On the other side, the use of complex parallel and heterogeneous embedded processor architectures becomes mandatory to cope with the performance requirements. In this regard, parallel programming models, such as OpenMP or CUDA, are a fundamental brick to fully exploit the performance capabilities of these architectures. However, parallel programming models are not compatible with current MDE approaches, creating a gap between the MDE used to develop CPSs and the parallel programming models supported by novel and future embedded platforms. The AMPERE project will bridge this gap by implementing a novel software architecture for the development of advanced CPSs. To do so, the proposed software architecture will be capable of capturing the definition of the components and communications described in the MDE framework, together with the non-functional properties, and transform it into key parallel constructs present in current parallel models, which may require extensions. These features will allow for making an efficient use of underlying parallel and heterogeneous architectures, while ensuring compliance with non-functional requirements, including those on real-time performance of the system. Index Terms-parallel programming models, parallel and heterogeneous embedded processor architectures, model-driven approaches, safety-critical embedded systems * This work has been supported by the EU H2020 project AMPERE under the grant agreement no. 871669.

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“…In an exact model, the WCET figure to be used depends on the schedule of tasks, which creates a circular dependence as WCET is also an input for deriving a feasible schedule. This issue has been initially tackled by an iterative approach to simultaneously attack WCET and scheduling [11]. With fTC the WCET estimate is not affected by the load contender tasks put on the shared resources, and hence it does not depend on task scheduling.…”

Section: Ptc Modelmentioning

confidence: 99%

MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding

Diaz

Fernandez

Kosmidis

et al. 2017

Reliable Software Technologies – Ada-Europe 2017

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Abstract. In critical domains, reliable software execution is increasingly involving aspects related to the timing dimension. This is due to the advent of high-performance (complex) hardware, used to provide the rising levels of guaranteed performance needed in those domains. Caches and multicores are two of the hardware features that have the potential to significantly reduce WCET estimates, yet they pose new challenges on current-practice measurement-based timing analysis (MBTA) approaches. In this paper we propose MC2, a technique for multilevel-cache multicores that combines deterministic and probabilistic jitter-bounding approaches to reliably handle both the variability in execution time generated by caches and the contention in accessing shared hardware resources. We evaluate MC2 on a COTS quad-core LEON-based board and our initial results show how it effectively captures cache and multicore contention in pWCET estimates with respect to actual observed values.

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Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

Cited by 9 publications

References 23 publications

Automatic Code Generation of Safety Mechanisms in Model-Driven Development

Automatic Code Generation of Safety Mechanisms in Model-Driven Development

The AMPERE Project: : A Model-driven development framework for highly Parallel and EneRgy-Efficient computation supporting multi-criteria optimization

MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding

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