Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation

Flores, Paulo; Costa, José Lino; Neto, Horácio C.; Monteiro, José; Marques-Silva, João

doi:10.1109/icvd.1999.745121

Cited by 45 publications

(29 citation statements)

References 13 publications

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“…In safety-critical applications, the electronics are frequently tested (the test might be even in-field and even online) by Built-in Self-Test (BIST) modules [Flores99]. Online testing, in particular, can consume a large part of the overall power budget.…”

Section: Test Reorderingmentioning

confidence: 99%

“…Online testing, in particular, can consume a large part of the overall power budget. A test ordering technique for power reduction is proposed in [Flores99]. The circuit-under-tests switching activities are approximated by Hamming distances between the subsequent tests.…”

Section: Test Reorderingmentioning

confidence: 99%

“…The problem is simplified so that an ILP technique can be used. Moreover, a Christofides algorithm is employed to find a low-power test order [Flores99].…”

Section: Test Reorderingmentioning

confidence: 99%

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Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deepsubmicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D-stacked-ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be accelerated using gradientbased, burn-in like operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. Schedule-based techniques that enforces the temperature-gradients for burn-in like operations and delay testing are proposed in this thesis. Abstract iiThe last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safetycritical systems to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC'02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the test costs. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the test schedule generation time by more than half.iii Populärvetenskaplig sammanfattningMånga banbrytande dator-och elektronikprodukter drivs...

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Section: Test Reorderingmentioning

confidence: 99%

Section: Test Reorderingmentioning

confidence: 99%

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Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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“…Consequently, several low power solutions targeting core-level design-for-test(DFT), as well as system-level DFT have been recently proposed. Techniques falling in the first category include low-power scan chain architectures with gated clocks [18,17], scan cell and test pattern reordering [3,5], and low-transition test patterns generated by specialised ATPG algorithms [22] and low-transition TPGs [21]. The second category of techniques is mainly based on powerconstrained test scheduling algorithms [2,9,11,7,6,1,15,12,13] 1 .…”

Section: Introductionmentioning

confidence: 99%

Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits

Rosinger

Al-Hashimi

Chakrabarty

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Several solutions have been developed for test planning during embedded core design, as well as during chip-level system integration. Techniques falling in the first category include low-power scan chain architectures with gated clocks [16,4,14], scan cell and test pattern reordering [3,5], and low-transition test patterns generated by specialized ATPG algorithms [19] and low-transition TPGs [18]. The second category of techniques is mainly based on power-constrained test scheduling algorithms [2,8,10,7,6,1,13,11,12] and the recently proposed thermal-safe test scheduling algorithms [15].…”

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confidence: 99%