Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits

Rosinger, P.; Al-Hashimi, B.M.; Chakrabarty, Krishnendu

doi:10.1109/tcad.2006.873898

Cited by 48 publications

(40 citation statements)

References 17 publications

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“…Test scheduling for non-stacked ICs to minimize the test time has been addressed in several publications [5,7,19,23,24,32]. While Samii et.…”

Section: Related Workmentioning

confidence: 99%

“…al. in [23] addressed test scheduling for core-based non-stacked ICs ensuring thermal safety, as a global power constraint may not take into account power density distribution, or core layout, thus limiting lateral heat removal. However, such test scheduling approaches require precise input data such as heat dissipation map and core layout, which are difficult to obtain.…”

Section: Related Workmentioning

confidence: 99%

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Test Planning for Core-based Integrated Circuits under Power Constraints

et al. 2017

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“…Test scheduling for non-stacked ICs to minimize the test time has been addressed in several publications [5,7,19,23,24,32]. While Samii et.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Test Planning for Core-based Integrated Circuits under Power Constraints

et al. 2017

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“…A category of efficient approaches that do not make the testing unnecessarily long are based on changing the test schedules [Rosinger06]. In order to prevent overheating during the test, temperature simulations are performed before the actual test during the scheduling process.…”

Section: Test Power and Temperaturementioning

confidence: 99%

“…This results in considerable variations in the temperature of the device and poses difficulties for the offline temperature-aware test scheduling techniques that are deterministic (e.g., [Rosinger06]). To handle this situation, stochastic approaches are proposed in this thesis in chapter 4.…”

Section: Test Power and Temperaturementioning

confidence: 99%

Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deepsubmicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D-stacked-ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be accelerated using gradientbased, burn-in like operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. Schedule-based techniques that enforces the temperature-gradients for burn-in like operations and delay testing are proposed in this thesis. Abstract iiThe last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safetycritical systems to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC'02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the test costs. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the test schedule generation time by more than half.iii Populärvetenskaplig sammanfattningMånga banbrytande dator-och elektronikprodukter drivs...

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“…There have been studies on a chip temperature minimization in testing [1,2,3,4,5,6,7,8,9,10,11]. Thermal-aware X filling techniques properly assign logic values to the X-bits to minimize circuit power as well as peak temperature [1,2,3].…”

Section: Introductionmentioning

confidence: 99%

Temperature and voltage droop-aware test scheduling during scan shift operation

Lee

Kim

Yang

2016

IEICE Electron. Express

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Hotspots and voltage droops have become critical problems during scan test. They are minimized by dynamically varying clock frequency during scan shift operation. We control average and peak temperature by adjusting the clock frequency assigned to each core. This proposed method is applied to multi-core System-on-Chip (SoC). Experimental results show that our method achieves 28% peak temperature reduction and 38% average temperature reduction.

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Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits

Abstract: Overheating has been acknowledged as a major problem during the testing of complex system-on-chip (SOC

Cited by 48 publications

References 17 publications

Test Planning for Core-based Integrated Circuits under Power Constraints

Test Planning for Core-based Integrated Circuits under Power Constraints

Thermal Issues in Testing of Advanced Systems on Chip

Temperature and voltage droop-aware test scheduling during scan shift operation

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