Astrocyte on neuronal phase synchrony in CMOS

Irizarry-Valle, Yilda; Parker, Alice C.

doi:10.1109/iscas.2014.6865115

Cited by 11 publications

(8 citation statements)

References 10 publications

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“…There have been promising implementations of astrocyte cells within neuromorphic circuitry [21, 22] and digital hardware devices [20, 23–27]. This work extends on the previous work by the authors [28] where a ring topology was used to communicate e‐SP (endocannabinoid‐mediated synaptic potentiation) from the astrocyte to associated synapses within hierarchical networks‐on‐chip (HNoC).…”

Section: Introductionmentioning

confidence: 75%

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On‐chip communication for neuro‐glia networks

Martin

Harkin

McDaid

et al. 2018

IET Computers & Digital Techniques

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Hardware has become more prone to faults as a result of geometric scaling, wear-out and faults caused during the manufacturing process, therefore, the reliability of hardware is reliant on the need to continually adapt to faults. A computational model of biological self-repair in the brain, derived from observing the role of astrocytes (a glial cell found in the mammalian brain), has captured self-repair within models of neural networks known as neuro-glia networks. This astrocyte-driven repair process can address the issues of faulty synapse connections between neurons. These astrocyte cells are distributed throughout a neuro-glia network and regulate synaptic activity, and it has been observed in computational models that this can result in a fine-grained self-repair process. Therefore, mapping neuro-glia networks to hardware provides a strategy for achieving self-repair in hardware. The internal interconnecting of these networks in hardware is a challenge. Previous work has focused on addressing neuron to astrocyte communication (local), however, the global self-repair process is dependent on the communication infrastructure between astrocyte-to-astrocyte; e.g. astrocyte network. This paper addresses the key challenge of providing a scalable communication interconnect for global astrocyte network requirements and how it integrates with existing local communication mechanism. Area/power results demonstrate scalable implementations with the ring topology while meeting timing requirements.

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Section: Introductionmentioning

confidence: 75%

“…as the PR increases the neurons activity will return to a pre‐fault level. This is evident when faults, including catastrophic failure (80% of faulty synapses), have been introduced into a neural network [21]. An SNN solely consists of neurons connected via synapses in a complex topology.…”

Section: Introductionmentioning

confidence: 99%

On‐chip communication for neuro‐glia networks

Martin

Harkin

McDaid

et al. 2018

IET Computers & Digital Techniques

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“…This group has presented several papers with new behaviors of astrocytes. They simulate reception of neurotransmitters by astrocytes [241] and the slow inwards currents caused in the neurons by the astrocytes [242,243]. The group is also developing BioRC carbon nanotube transistors [244][245][246][247][248][249][250][251] to simulate neuromorphic circuits.…”

Section: Biorcmentioning

confidence: 99%

Parallel Computing for Brain Simulation

Pastur-Romay

Porto-Pazos

Cedrón

2017

CTMC

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This paper presents an up-to-date review about the main research projects that are trying to simulate and/or emulate the human brain. They employ different types of computational models using parallel computing: digital models, analog models and hybrid models. This review includes the current applications of these works, as well as future trends. It is focused on various works that look for advanced progress in Neuroscience and still others which seek new discoveries in Computer Science (neuromorphic hardware, machine learning techniques). Their most outstanding characteristics are summarized and the latest advances and future plans are presented. In addition, this review points out the importance of considering not only neurons: Computational models of the brain should also include glial cells, given the proven importance of astrocytes in information processing.

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“…Recent work has implemented astrocyte cells in neuromorphic systems [8], [9] and digital circuits [10]- [13] with the aim of exploring their behaviour. None have considered the challenge of facilitating scalable interconnect for neuro-glia networks.…”

Section: From Biology To Hardwarementioning

confidence: 99%

Astrocyte to spiking neuron communication using Networks-on-Chip ring topology

Martin

Harkin

McDaid

et al. 2016

2016 IEEE Symposium Series on Computational Intelligence (SSCI)

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Hardware faults are becoming more frequent due to geometric scaling, reducing the reliability and lifespan of devices. Current fault-tolerant approaches use redundancy or a central controller to detect and/or repair faults. However, these methods are also susceptible to faults. Astrocytes have been shown to facilitate biological self-repair in silent or near silent neurons in the brain by increasing the Probability of Release (PR) in healthy synapses. Astrocytes modulate synaptic activity, which leads to increased or decreased PR. To date, this has been proven with computational modelling and therefore the next step is to replicate this self-repair process in hardware to provide self-repairing systems. One of the key challenges for hardware neuro-glia networks is the facilitation of scalable communication between interacting neurons and astrocyte cells. This paper contributes a low-level Networks-on-Chip (NoC) ring topology for astrocyte to neuron/synapse communication which provide a scalable solution to this interconnect challenge. This work extends our current FPGA-based Hierarchical Networks-on-Chip (HNoC). FPGA results demonstrates that the new ring topology provides a good trade-off between low area/interconnect wiring overhead and communication speed for the relatively slow-changing data between astrocyte and neurons.

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Astrocyte on neuronal phase synchrony in CMOS

Cited by 11 publications

References 10 publications

On‐chip communication for neuro‐glia networks

On‐chip communication for neuro‐glia networks

Parallel Computing for Brain Simulation

Astrocyte to spiking neuron communication using Networks-on-Chip ring topology

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