Asymmetric Aging: Introduction and Solution for Power-Managed Mixed-Signal SoCs

CSAM: A clock skew-aware aging mitigation technique

“…In the proposed technique in this work, by selecting a proper ICG cell, we either increase or decrease the clock skew such that the objective function is best satisfied (see (8), (9), and (10)). To show the approach, for the case of the first objective function, we have depicted the minimum and maximum clock skews for both the CSAM and conventional techniques in Fig.…”

“…If, however, the gating technique is invoked, the asymmetric aging causes some additional clock skew in the network. The effects of asymmetric aging due to usage of clock gating schemes are discussed in [9,10,[13][14][15].…”

“…The problem of asymmetric aging with a special focus on clock skew, pulse width, and aspects of burn-in is discussed in [9]. A timing analysis framework based on SSTA is presented for asymmetric aging analysis and mitigation of NBTI induced degradation on clock skew.…”

“…This causes asymmetric aging rate which induces a non-uniformity in the timing rendered by the clock tree at different parts of the chip. The effects of asymmetric NBTI induced aging on the reliability (lifetime) of the logic path and clock tree circuits have been studied and techniques to improve the reliability have been suggested (see, e.g., [9,10]). To the best of our knowledge, these techniques, however, have focused either only on the logic path (neglecting the NBTI effect on the clock tree part) or on the clock tree part (ignoring the NBTI effect on the logic path circuit).…”

Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits

“…As mentioned before, different workload conditions in different periods of the circuit lifetime may lead to unequal aging rates for different parts of the circuit. The asymmetric aging due to the workload dependency would show themselves more clearly when power management techniques such as clock gating schemes are invoked [11,18,19]. This has been the motivation for proposing some aging mitigation technique for reducing the effect of the asymmetric aging on circuit timing by simultaneous consideration of NBTI-induced degradation on clock tree and logic path [15].…”