2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) 2018
DOI: 10.1109/asmc.2018.8373146
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Asymmetric etching profile control during high aspect ratio Plasma etch

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“…Charges were trapped in bottom N/O film layers during CH etch process and lead to etch plasma tilt which cause CSL slit tilting (figure 5). After the long-time CH etching process, positive ion charges were accumulated near the bottom layers [14,17] and would trapped in bottom N/O films. After that, charges would accumulate around CH in poly-Si channels deposited process due to antenna effect [22,23].…”
Section: Methodsmentioning
confidence: 99%
See 1 more Smart Citation
“…Charges were trapped in bottom N/O film layers during CH etch process and lead to etch plasma tilt which cause CSL slit tilting (figure 5). After the long-time CH etching process, positive ion charges were accumulated near the bottom layers [14,17] and would trapped in bottom N/O films. After that, charges would accumulate around CH in poly-Si channels deposited process due to antenna effect [22,23].…”
Section: Methodsmentioning
confidence: 99%
“…In order to study the causes of this issue and eliminate its impact, the charging model [8,[14][15][16][17] was proposed to explain the causes of the phenomena shown in the figure 1. It is ion charges trapped in N/O films that distorted the plasma in the etch process, which caused the plasma to tilt and then CSL tilted to one side.…”
Section: Introductionmentioning
confidence: 99%