Asymmetric monotonic switching scheme for energy-efficient SAR ADCs

Abstract

Asymmetric monotonic switching scheme is proposed for a low power successive approximation register (SAR) analogue-to-digital converter (ADC). The proposed switching procedure consumes no energy from reference voltage for the first 3 MSB (most significant bit) conversion using unequal initial DAC setting and asymmetric binary search algorithm. After 3 MSB conversions, DAC switching utilizes a conventional monotonic DAC switching for further energy saving. As a result, average energy saving during conversion cycles has been improved up to 98.5% as compared with conventional architectures.

Strategy for SAR ADC with 87.5% area saving and 99.4% switching energy reduction over conventional approach

“…2b shows the proposed capacitor array. Consequently, for N-bit SAR ADC, the number of capacitors Num can be reduced to: It is approximately 2Â reduction over the schemes proposed in [3,4,5,6], that is, 8Â reduction over the conventional approach.…”

“…The MCS scheme of [3] and tri-level scheme of [4] can reach a reduction of 93.7%, 96.9%, respectively. The Vcm-based monotonic scheme of [5], asymmetric monotonic switching scheme of [6] and the mixed switching scheme [7] can reach a reduction of 97.7%, 98.5% and 87.5%, separately. However, with this proposed switching scheme, the switching energy and the chip area required can be reduced by 98.8% and 75% separately.…”

“…During the past several years, great efforts have been made to develop energy-efficient switching schemes for SAR ADCs to reduce the switching energy [1,2,3,4,5,6]. Compared to the conventional switching scheme, the set-and-down scheme of [1] and Vcm-based scheme of [2] realize a reduction of 81.2% and 87.5% separately in switching power.…”

Variable resolution SAR ADC architecture with 99.6% reduction in switching energy over conventional scheme

“…Recent state-of-the-art has introduced several techniques to reduce the switching energy. Compared to the conventional architecture, the new tri-level [1], Sanyal and Sun [2], asymmetric monotonic [3] and hybrid capacitor [4] reduce the switching energy by 96.89%, 98.4%, 98.5% and 98.83%, respectively. The switching architecture in [5] employing the previous bits to control the splitting capacitors of the sub-DAC has significant energy consumption from the first two comparison cycles, and wastes the same large capacitor area as the conventional scheme.…”

An energy‐efficient switching scheme based on distributing most significant bit capacitors for successive approximation register analog‐to‐digital converter

“…1,2 However, as the conversion resolution increases, the capacitance of the digital-to-analog converter (DAC) array in the SAR ADC will increase exponentially, hence a sharp increase in the area and power consumption of the DAC array. [3][4][5] In the past few years, various energy-efficient switching schemes, including monotonic, 6 V CM based, 7 trilevel, 8 VMS, 9 and hybrid, 10 have been emerging, making a breakthrough in the low power consumption research of SAR ADC. Compared with the traditional capacitor switching scheme, the monotonic technology reduces the switching energy by 81.2% and the V CM -based technology by 87.5%.…”