An energy‐efficient switching scheme based on distributing most significant bit capacitors for successive approximation register analog‐to‐digital converter

Yu, Zhiguo; Wang, Tao; Song, Xinyu; Tian, Wenhan; Liu, Kangsheng; Gu, Xiaofeng

doi:10.1002/cta.2941

Cited by 3 publications

(5 citation statements)

References 13 publications

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“…Instead of handling the CDAC array, distribution of one capacitor splitting technique may be sufcient. Te MSB splitting technique, the MSB capacitor is divided into binaryweighted capacitors as shown in Figure 13, is the most popular technique [11,12,22,25,[38][39][40][41][42][43][44][45][46]. Te power is saved by up to 37% as reported in [25].…”

Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

“…Tese schemes include the two-level, three-level and four-level voltage switching schemes. Two-level voltage switching schemes have been used in [41,44,57,[69][70][71][72][73] to improve the power consumption and enhance the stability and accuracy of CDAC. Higher precision and linearity can be obtained with lower average switching energy by employing two-level voltages.…”

Section: Cdac Voltage Switching Schemesmentioning

confidence: 99%

“…Regardless of the precision of Vcm, the linearity has been enhanced by using intermediate step in this scheme. Additionally, to avoid using Vcm, the replacement dummy capacitor, an array of the capacitors is proposed in [44]. Several works [16,26,38,43,46,51,[74][75][76][77][78][79][80][81][82][83][84][85][86][87] utilized the three level voltages (gnd, Vref, Vcm) to reduce the area of CDAC and relax the capacitor matching requirement without adding other switches.…”

Section: Cdac Voltage Switching Schemesmentioning

confidence: 99%

“…To improve the speed and power consumption of SAR ADC, an asynchronous scheme [7,11,16,17,24,35,44,53,58,64,86,91] is employed, as shown in Figure 35. Also, the complexity and area of SAR control logic are minimized.…”

Section: Sar Register and Its Control Logicmentioning

confidence: 99%

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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

Section: Cdac Voltage Switching Schemesmentioning

confidence: 99%

Section: Cdac Voltage Switching Schemesmentioning

confidence: 99%

Section: Sar Register and Its Control Logicmentioning

confidence: 99%

See 2 more Smart Citations

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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show abstract

“…17,18 The tri-level switching scheme reduces the switching energy by more than 93.7% and achieves 75% reduction in total capacitor size. 19 The scheme in previous works 20 by distributing MSB capacitor into two parallel binary-weighted capacitor can save switching energy by up to 95.93%. The charge sharing technique is utilized in previous works [21][22][23] to completely save the DAC's switching energy.…”

Section: Introductionmentioning

confidence: 99%

A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

Pahlavanzadeh

Karami

2023

Circuit Theory & Apps

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Summary This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM.

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A Low-Power SAR ADC with Multi-mode Switching Scheme

Zhang,

Xu,

2023

2022 10th International Symposium on Next-Generation Electronics (ISNE)

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An energy‐efficient switching scheme based on distributing most significant bit capacitors for successive approximation register analog‐to‐digital converter

Cited by 3 publications

References 13 publications

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

A Low-Power SAR ADC with Multi-mode Switching Scheme

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