Asymmetrical 21‐level inverter topology with minimum variety of dc sources and reduced component counts

Abstract

This paper proposes an asymmetrical multilevel inverter (MLI) topology. The inverter utilizes 12 switches, four dc sources, and two diodes to generate 21 levels. The main advantage of the converter is that it can generate 21 levels with a reduced number of switches, dc sources, and a variety of sources compared with other MLI topologies. It only utilizes two varieties of dc sources to generate the 21 levels. In addition, the topology can be easily extended to the n-level topology. The efficiency of the proposed MLI is determined by considering switching and conduction losses in the switches using PLECS, and simulation is carried out in MATLAB/SIMULINK. The nearest level control (NLC) technique is deployed to generate the switching signals. The inverter has 3.91% THD in the output voltage without filtering. The maximum voltage stress to withstand is found to be 0.7 per unit. Economic analysis of the topology is done to determine its feasibility, and the cost factor is found to be 1.53 per level, making it an economically viable option. To validate the performance of the proposed converter, an experimental prototype is developed in the laboratory and tested under different loading conditions. The comparison of the proposed topology with other MLI structures is based on the number of voltage levels, dc sources, variety of sources, driver circuits, and the TSV. Results obtained show that the proposed topology outperformed other topologies on many parameters.