Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs

Jain, Tushar Naveen Kumar; Gratz, Paul V.; Sprintson, Alex; Choi, Gwan

doi:10.1109/nocs.2010.15

Cited by 19 publications

(14 citation statements)

References 16 publications

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“…Link improvement: Low-swing signalling [20] and an asynchronous link [21,22] have been adopted in NoCs to allow multiple-hop traversal in one cycle. Low-swing signalling has poor bandwidth density, and the asynchronous link can have signal skew issues due to interference [23].…”

Section: Noc Router Architecture and Algorithmsmentioning

confidence: 99%

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Agyeman

Zong

Yakovlev

et al. 2017

JLPEA

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Abstract:To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cost-effective solution for emerging system-on-chip (SoC) design. However, these interconnects trade off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in a chip multiprocessor (CMP) demands an on-chip communication infrastructure that can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that the proposed router can reduce applications' execution time by an average of 16.9% compared to low-latency routers, such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can improve the performance efficiency in terms of average packet delay by an average of 45% (or 50%) in 3D NoCs (or WiNoCs).

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Section: Noc Router Architecture and Algorithmsmentioning

confidence: 99%

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Agyeman

Zong

Yakovlev

et al. 2017

JLPEA

View full text Add to dashboard Cite

show abstract

“…Low-swing signaling [10] and asynchronous link [11,12] have been adopted in NoC to allow multiple-hop traversal in one cycle. Low-swing signaling has poor bandwidth density, and asynchronous link can have signal skew issues due to interference [13].…”

Section: Related Workmentioning

confidence: 99%

On Improving the Performance of Hybrid Wired-Wireless Network-on-Chip Architectures

Zong

Agyeman

2016

Proceedings of the 9th International Workshop on Network on Chip Architectures

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Recently, hybrid wired-wireless Network-on-Chip (WiNoC) have been proposed to meet the performance and scalability demands of modern System-on-Chip (SoC) design. However, due to the presence of wirelines with multi-hop nodes in the hybrid architecture, WiNoCs have reduced performance efficiency. In this paper, we propose a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation in such emerging hybrid NoCs. The proposed router employs both dimension-ordered routing (DoR) and a deadlock free adaptive routing to transmit flits at lowloads and high traffic loads, respectively, to efficiently balance traffic in WiNoCs. By reducing the latency between the wired nodes and the wireless nodes, the proposed router can improve performance efficiency in terms of average packet delay by an average of 45% (or 50%) in WiNoCs.

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“…In [17], the authors propose an reconfigurable NoC architecture to minimize latency and energy overhead under a DVFS technique. In [18], the authors propose asynchronous bypass channels to improve the performance of DVFS enabled NoC.…”

Section: Related Workmentioning

confidence: 99%

A Buffer‐Sizing Algorithm for Network‐on‐Chips with Multiple Voltage‐Frequency Islands

Kumar

Murali³

et al. 2012

Journal of Electrical and Computer Engineering

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Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem. Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuniformity. Also, congestion effects that occur during network operation need to be captured when sizing the buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking place through frequency converters. To this end, we propose a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency islands. Our algorithm considers both the static and dynamic effects when sizing buffers. We analyze the impact of placing frequency converters (FCs) on a link, as well as pack and send units that effectively utilize network bandwidth. Experiments on many realistic system-on-Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach.

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Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs

Cited by 19 publications

References 16 publications

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

On Improving the Performance of Hybrid Wired-Wireless Network-on-Chip Architectures

A Buffer‐Sizing Algorithm for Network‐on‐Chips with Multiple Voltage‐Frequency Islands

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