Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Abstract

Abstract:To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cost-effective solution for emerging system-on-chip (SoC) design. However, these interconnects trade off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in a chip multiprocessor (CMP) demands an on-chip communication infrastructure that can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that the proposed router can reduce applications' execution time by an average of 16.9% compared to low-latency routers, such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can improve the performance efficiency in terms of average packet delay by an average of 45% (or 50%) in 3D NoCs (or WiNoCs).

Exploration on Routing Configuration of HNoC With Intelligent On-Chip Resource Management

“…To ensure the cooperative work among units of HNoC, the communication quality among units are essential, because the communication characteristics of CPU and GPU are totally different [6], [8]. CPUs are designed to use complex control logics to allow a single thread to execute instructions in parallel (even for unordered instructions) on the premise of keeping the application executed on demands as a whole.…”

NOC’S: Buffered and Bufferless Structure and their design methodologies for High throughput and Low latency

“…The simulation depicts that the proposed router can reduce the execution time of applications by an average of 16.9% in contrast to low-latency routers, such as SWIFT. By decreasing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can enhance the performance efficiency in terms of average packet delay by an average of 45% (or 50%) in 3D NoCs (orWiNoCs) [31].…”

Traffic-aware performance optimization in Real-time wireless network on chip

“…These approaches cannot cover RT constraints, which are crucial for real-time systems; hence they do not cover all the challenging aspects of WNoC performance. On the other hand, the few works that deal with QoS in WNoC [10][11][12][13][14] do not consider average parameters simultaneously with their worst-case counterparts. These approaches have concentrated on the RT flows and have not considered the performance parameters of NRT flows in the network.…”