Asynchronous Circuit Designs for the Internet of Everything: A Methodology for Ultralow-Power Circuits with GALS Architecture

Beigné, Edith; Vivet, Pascal; Thonnart, Yvain; Christmann, Jean-Frédéric; Clermidy, Fabien

doi:10.1109/mssc.2016.2573864

Cited by 20 publications

(8 citation statements)

References 20 publications

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“…Finally, as the AR part is based on a programmable core architecture, it can adaptively configure OD triggering conditions to limit the false detections. In [25], an asynchronous circuit design methodology is described for ultra-low power systems. The authors evaluate the gains of an asynchronous wake-up controller on the alwaysresponsive sub-system.…”

Section: L-iot Approach and Samurai Proposalmentioning

confidence: 99%

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration

Miro-Panades

Tain

Christmann

et al. 2023

IEEE J. Solid-State Circuits

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Increased capabilities such as recognition and selfadaptability are now required from IoT applications. While IoT node power consumption is a major concern for these applications, cloud-based processing is becoming unsustainable due to continuous sensor or image data transmission over the wireless network. Thus optimized ML capabilities and data transfers should be integrated in the IoT node. Moreover, IoT applications are torn between sporadic data-logging and energy-hungry data processing (e.g. image classification). Thus, the versatility of the node is key in addressing this wide diversity of energy and processing needs. This paper presents SamurAI, a versatile IoT node bridging this gap in processing and in energy by leveraging two on-chip sub-systems: a low power, clock-less, event-driven Always-Responsive (AR) part and an energy-efficient On-Demand (OD) part. AR contains a 1.7MOPS event-driven, asynchronous Wake-up Controller (WuC) with a 207ns wake-up time optimized for sporadic computing, while OD combines a deep-sleep RISC-V CPU and 1.3TOPS/W Machine Learning (ML) for more complex tasks up to 36GOPS. This architecture partitioning achieves best in class versatility metrics such as peak performance to idle power ratio. On an applicative classification scenario, it demonstrates system power gains, up to 3.5x compared to cloud-based processing, and thus extended battery lifetime.

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Section: L-iot Approach and Samurai Proposalmentioning

confidence: 99%

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration

Miro-Panades

Tain

Christmann

et al. 2023

IEEE J. Solid-State Circuits

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“…The event-driven scheme provides robustness to operating parameters such as temperature, supply voltage level, or process variations, while implementing automatic sleep mode (i.e., clock-gated mode in synchronous circuits). These advantages make asynchronous QDI circuits highly suitable for low power applications such as the Internet of Things [9]. While the dual-rail encoding is used to implement the four-phase handshake protocol, mixing data and request, bundled-data implementation may be used to allow lighter binary encoding.…”

Section: Asynchronous Wake Up Controller Architecturementioning

confidence: 99%

A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

Christmann

Berthier

Coriat

et al. 2019

JLPEA

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Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 ns@9.2 Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm.

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“…As mentioned previously, we used asynchronous logic [22] to implement the asynchronous service network. It allows us to achieve a plug-and-play implementation and avoid power domain crossing problems common to many SoC circuits [23], since we no longer have to worry about timing problems.…”

Section: Network's Micro-architecturementioning

confidence: 99%

Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

Chairat¹,

Beigné²,

Miro-Panades³

et al. 2017

JLPEA

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This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit's architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL) to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI) technology at 0.6 V and a 1.1 ns/bit latency per stage.

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Asynchronous Circuit Designs for the Internet of Everything: A Methodology for Ultralow-Power Circuits with GALS Architecture

Cited by 20 publications

References 20 publications

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration

A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

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