Asynchronous Circuit Designs on an FPGA for Targeting a Power/Energy Efficient SoC

Lee, Jeong-Gun; Oh, Myeong‐Hoon

doi:10.1587/transele.e97.c.253

Cited by 2 publications

(1 citation statement)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Also, if the designers make gate chain, the optimizer easily remove that logic. Owing to accomplish matching the delays of the respective data path, the designers need to make user specific delay cells by invoking the LUT gates [30] with "KEEP" constraints. After that, the designers require to measure the delay of written LUT gates manually on the post-route simulation level since, the timing of written LUT based delay cell would vary, depending on which FPGA model was used.…”

Section: Proposed Design Techniquesmentioning

confidence: 99%

Implementation of an Asynchronous Micro-controlleron the Commercial FPGA

Shin¹,

Oh²,

Kwon³

et al. 2017

IJCTE

Self Cite

View full text Add to dashboard Cite

Abstract-An asynchronous circuit design methodology has been introduced as a novelty approach to future digital system design. Nevertheless, in order to implement the asynchronous circuit, there are various limitations. Especially, for the implementation on a commercialized field programmable gate array (FPGA), the vendors and design tools mainly support only synchronous circuit design. In this paper, we propose design techniques for implementing the asynchronous circuit on the commercial FPGA using the provided design tool. Then, with the proposed design techniques, we designed an asynchronous micro-controller based onaTIMSP430 instruction set architecture (ISA).We observe that the asynchronous core consumes lower power than the synchronous one. In addition, the asynchronous core also shows much more durability under conditions of unstable power supplies compared to the synchronous counterpart.Index Terms-Asynchronous circuit, AFSM, bounded delay, FPGA.

show abstract

Section: Proposed Design Techniquesmentioning

confidence: 99%