Asynchronous Current Mode Serial Communication

Dobkin, Rostislav; Moyal, M.; Kolodny, Avinoam; Ginosar, Ran

doi:10.1109/tvlsi.2009.2020859

Cited by 36 publications

(13 citation statements)

References 44 publications

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“…In addition, devices implementing serial communication have an asynchronous clock that drives those protocols (e.g. Dobkin et al, 2010). If this clock is correlated with the device's sampling clock, the receiving data logger can -at least in principle -reconstruct the sampling clock.…”

Section: The Problem Of Clocks Synchronization In Digital Systemsmentioning

confidence: 99%

Eddy Covariance flux errors due to random and systematic timing errors during data acquisition

Fratini¹,

Sabbatini²,

Ediger³

et al. 2018

Preprint

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Abstract. Modern Eddy Covariance (EC) systems collect high-frequency data (10-20 Hz) via instruments' digital outputs.While this helps overcome the limits of traditional mixed analog/digital systems, it also introduces the new problem of guaranteeing data synchronicity when the clocks of the involved devices cannot themselves be synchronized, which is often 10 the case with instruments providing data via serial or Ethernet connectivity. By means of a simulation study, we found that in most cases random timing errors can safely be neglected, as they don't impact fluxes to a large extent. On the contrary, realistic systematic timing errors potentially arising in asynchronous systems can lead to flux underestimations as large as 10%, by means of attenuation of high-frequency flux contributions. We characterize the transfer function of such filters as a function of the error amount and find cut-off frequencies as low as 1 Hz, which means that synchronization errors can 15 dominate high-frequency attenuations in open-and enclosed-path EC systems. In most cases, such timing errors cannot be detected nor quantified a posteriori. Therefore, we suggest testing the ability of prospect EC data logging systems to assure required synchronicity and propose a procedure to implement such a test which relies on readily available equipment.

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Section: The Problem Of Clocks Synchronization In Digital Systemsmentioning

confidence: 99%

Eddy Covariance flux errors due to random and systematic timing errors during data acquisition

Fratini¹,

Sabbatini²,

Ediger³

et al. 2018

Preprint

View full text Add to dashboard Cite

show abstract

“…In [12], [13], high-speed serial links have been reported based on a burst-mode data transmission scheme [18]- [20]. In the burst-mode data-transmission method, a word that contains several tens of bits is transmitted without the perbit handshake unlike the communication links based on the QDI logic style.…”

Section: Related Workmentioning

confidence: 99%

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

Onizawa

Mochizuki

Shirahama

et al. 2014

IEICE Trans. Inf. & Syst.

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“…This enables robustness to delay variations through the use of delay-insensitive encoding and data transfer. A single gate delay data cycle asynchronous bit-serial link has been initially presented in [23] and its improved version in [43]. It uses two-phase level-encoded dual-rail (LEDR) data encoding, fast asynchronous shift registers for both serializer and deserializer and wave-pipelined differential signaling.…”

Section: Related Workmentioning

confidence: 99%

Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput

Nigussie

Tuuna

Plosila

et al. 2012

IEEE Trans. VLSI Syst.

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A high-throughput and low-energy semi-serial on-chip communication link based on novel design techniques and circuit solutions is presented. This self-timed link is designed using high-speed serialization/deserializtion and pulse dual-rail encoding techniques. The link also employs wave-pipelined differential pulse current-mode signaling to maintain the high speed data intake from the serializer. The energy efficiency of the proposed semi-serial link, which consists of bit-serial links in parallel, mainly comes from the sharing of the novel serializer's control circuit among the bit-serial links. In addition, the integration of pulse signaling with wave-pipelining, the use of a new low-complexity data validity detection technique, and the avoidance of data decoding logic also contribute to the power reduction. Furthermore, the formulated pulse dual-rail encoding provides an opportunity to implement pulse signaling at no cost. The ability to detect data validity at bit level allows acknowledgment per word without losing the delay-insensitivity of the transmission. The proposed semi-serial link is analyzed and compared with bit-serial and fully bit-parallel links for 64-bit data and communication distances of 1 to 8 mm. The semi-serial link which consists of eight bit-serial links provides 72.72 Gbps throughput with 286 fJ/bit energy dissipation for 8 mm transmission. It dissipates the lowest energy per bit compared to fully bit-parallel links while achieving the same throughput. The links are designed and simulated in Cadence Analog Spectre using 65-nm technology from STMicroelectronics.

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Asynchronous Current Mode Serial Communication

Cited by 36 publications

References 44 publications

Eddy Covariance flux errors due to random and systematic timing errors during data acquisition

Eddy Covariance flux errors due to random and systematic timing errors during data acquisition

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput

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