Asynchronous on-chip networks

Amde, Manish; Felicijan, Tomaz; Efthymiou, A.; Edwards, Doug; Lavagno, Luciano

doi:10.1049/ip-cdt:20045093

Cited by 37 publications

(3 citation statements)

References 21 publications

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“…Abstraction of these models can alleviate this problem but at the prize of imprecise results. ESTEREL and SIGNAL are two synchronous languages that seem very appropriate to model and verify ANOC, since they implement well the GALS philosophy [40]. The Architecture Analysis & Design Language (AADL) is another good candidate for NOC simulation and formal verification.…”

Section: Discussionmentioning

confidence: 99%

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Boutekkouk

2018

Int. J. Recent Contrib. Eng. Sci. IT

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Network-On-Chip (NOC) is an emerging paradigm to surmount traditional bus based Systems-On-Chip (SOC) limits especially scalability and communication performances. A NOC includes many applications that can execute concurrently. This situation may show some undesirable behaviors such as deadlock, livelock, starvation, etc. On the other hand, the application of formal methods to on-chip communication infrastructures has recieved more attention. Formal analysis of NOC communication will be very advantageous since it allows proving some theorems or interesting qualitative/quantitative properties on the communication behavior where simulation/emulation techniques can fail easily. In this paper we try to giva an overview of the most famous formal methods applied to the verification of communication inside NOCs.

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Section: Discussionmentioning

confidence: 99%

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Boutekkouk

2018

Int. J. Recent Contrib. Eng. Sci. IT

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“…Mesochronous timing is a special form of globally asynchronous locally synchronous (GALS) timing (Dally & Poulton, 1997), in which different components run with the same frequency but unknown phase differences. The utilization of GALS timing for the NoC design provides significant improvement in design efficiency and power efficiency compared to synchronous design (Amde, Felicijan, Efthymiou, Edwards, & Lavagno, 2005), by eliminating the need of a global clock. Mesochronous NoC architecture is widely used in existing NoC prototypes, for instance the 80-tile Intel TeraFLOPS processor (Vangal et al, 2008).…”

Section: Introductionmentioning

confidence: 99%

Dual Monitoring Communication for Self-Aware Network-on-Chip

Plosila

Guang

Nigussie

et al. 2012

International Journal of Adaptive, Resilient and Autonomic Systems

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Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

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“…This mesh topology was selected for its modularity and scalability (it avoids long and global communication lines) and because it is the kind of layout typically used in cellular computing applications. Of course, many different types of networking paradigms exist and could be implemented in our system (for example [11], [16] or [1]). …”

Section: Transport Layer -The Mercury Interfacementioning

confidence: 99%

A Hardware-Software Design Framework for Distributed Cellular Computing

Mudry

Ruffin

Ganguin

et al. 2008

Evolvable Systems: From Biology to Hardware

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Abstract. In this article, we describe a novel hardware-software design framework for prototyping cellular architectures in hardware. Based on an extensible platform of about 200 FPGAs, configured as a networked structure of processors, the hardware part of this computing framework is backed by an extensible library of software components that provides primitives for efficient inter-processor communication and distributed computation. This dual software-hardware approach allows a very quick exploration of different ways to solve computational problems using bio-inspired techniques. To demonstrate the validity of the method, we present an example of how a traditional parallel system such as a cellular automaton can be modeled and run with this perspective. In addition, we also show that the flexibility of our approach allows not only cellular automata but any computation to be easily implemented on a cellular substrate.

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Asynchronous on-chip networks

Cited by 37 publications

References 21 publications

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Dual Monitoring Communication for Self-Aware Network-on-Chip

A Hardware-Software Design Framework for Distributed Cellular Computing

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