At-speed Test of High-Speed DUT Using Built-Off Test Interface

Park, Joon Sung; Lee, Jae Woo; Chung, Jaeyong; Han, Kihyuk; Abraham, Jacob A.; Byun, Eonjo; Woo, Cheol-Jong; Oh, Se-Jang

doi:10.1109/ats.2010.54

Cited by 7 publications

(2 citation statements)

References 9 publications

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“…The main reason of success of the memory BIST has been the simplicity of generating deterministic tests coupled with simple and regular structures of test generation schemes. In the same time, current logic BIST techniques based on using pseudorandom patterns remain mostly impractical due to low fault coverage, associated hardware overhead, performance degradation and excessive power consumption [13].…”

Section: State-of-the-artmentioning

confidence: 99%

At-Speed Functional Built-In Self-Test Methodology for Processors

Ubar

Indus²,

Kalmend³

2012

Engineering and Applied Science

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Dependability of systems has become one of the most important engineering concerns. With new technologies new paradigms of testing are emerging. One of them is to make systems self-testing, and the quality of self-test is the key issue. In this paper, a new methodology of functional Built-In Self-Test is proposed, which stresses testing in dynamics to achieve the highest fault coverage. The main novelty of the proposed approach is in using the inherent functionality of systems for testing them at-speed in normal working conditions. The proposed self-test includes on-chip test application and response collection by using the native instructions of the processor under test. A hierarchical divide-and-conquer approach is applied. At component level, tests are targeting structural faults in components whereas at processor level, the functionality of the processor is used to apply structural tests to each component at-speed. Differently from similar approaches, the sequences of component test patterns are not needed to store in the chip under test, they will be generated on-line by the resources of the system. A framework for synthesis of self-test stimuli data is proposed.

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Section: State-of-the-artmentioning

confidence: 99%

At-Speed Functional Built-In Self-Test Methodology for Processors

Ubar

Indus²,

Kalmend³

2012

Engineering and Applied Science

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“…Recently, it has been proposed to use a built-off-test (BOT) or built-off-self-test (BOST) module as a cost-effective method for the at-speed testing of high-speed memory ICs [3][4][5]. As shown in Figure 1, the BOT (or BOST) module is used as a bridge connecting the DUT and the ATE.…”

Section: Introductionmentioning

confidence: 99%

A Cost-Effective and Compact All-Digital Dual-Loop Jitter Attenuator for Built-Off-Test Applications

2022

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A compact and low-power all-digital CMOS dual-loop jitter attenuator (DJA) for low-cost built-off-test (BOT) applications such as parallel multi-DUT testing is presented. The proposed DJA adopts a new digital phase interpolator (PI)-based clock recovery (CR) loop with an adaptive decimation filter (ADF) function to remove the jitter and phase noise of the input clock, and generate a phase-aligned clean output clock. In addition, by adopting an all-digital multi-phase multiplying delay-locked loop (MDLL), eight low-jitter evenly spaced reference clocks that are required for the PI are generated. In the proposed DJA, both the MDLL and PI-based CR are first-order systems, and so this DJA has the advantage of high system stability. In addition, the proposed DJA has the benefit of a wide operating frequency range, unlike general PLL-based jitter attenuators that have a narrow frequency range and a jitter peaking problem. Implemented in a 40 nm 0.9 V CMOS process, the proposed DJA generates cleaned programmable output clock frequencies from 2.4 to 4.7 GHz. Furthermore, it achieves a peak-to-peak and RMS jitter attenuation of –25.6 dB and –32.6 dB, respectively, at 2.4 GHz. In addition, it occupies an active area of only 0.0257 mm2 and consumes a power of 7.41 mW at 2.4 GHz.

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