ATLAS: A Chip-Multiprocessor with Transactional Memory Support

Njoroge,; Casper, Casper; Wee,; Teslyar,; Ge, Ge; Kozyrakis,; Olukotun,

doi:10.1109/date.2007.364558

Cited by 28 publications

(21 citation statements)

References 22 publications

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“…Both industry and academia have relied on architectural simulators [5,13,10,3,7,16,11] in system architecture design, software development and performance evaluation during past decades. Mambo [4] is IBM's full-system simulator which models the PowerPC-based [8] systems, and provides a complete set of simulation tools to help IBM and its partners in pre-hardware development and performance evaluation for future systems [15,1,6,14].…”

Section: Introductionmentioning

confidence: 99%

Parallelization of IBM mambo system simulator in functional modes

Wang

Shen

2008

SIGOPS Oper. Syst. Rev.

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Mambo [4] is IBM's full-system simulator which models PowerPC systems, and provides a complete set of simulation tools to help IBM and its partners in pre-hardware development and performance evaluation for future systems. Currently Mambo simulates target systems on a single host thread. When the number of cores increases in a target system, Mambo's simulation performance for each core goes down. As the so-called "multi-core era" approaches, both target and host systems will have more and more cores. It is very important for Mambo to efficiently simulate a multicore target system on a multi-core host system. Parallelization is a natural method to speed up Mambo under this situation.Parallel Mambo (P-Mambo) is a multi-threaded implementation of Mambo. Mambo's simulation engine is implemented as a user-level thread-scheduler. We propose a multischeduler method to adapt Mambo's simulation engine to multi-threaded execution. Based on this method a corebased module partition is proposed to achieve both high inter-scheduler parallelism and low inter-scheduler dependency. Protection of shared resources is crucial to both correctness and performance of P-Mambo. Since there are two tiers of threads in P-Mambo, protecting shared resources by only OS-level locks possibly introduces deadlocks due to user-level context switch. We propose a new lock mechanism to handle this problem. Since Mambo is an on-going project with many modules currently under development, co-existence with new modules is also important to P-Mambo. We propose a global-lock-based method to guarantee compatibility of P-Mambo with future Mambo modules.We have implemented the first version of P-Mambo in functional modes. The performance of P-Mambo has been evaluated on the OpenMP implementation of NAS Parallel Benchmark (NPB) 3.2 [12]. Preliminary experimental results show that P-Mambo achieves an average speedup of 3.4 on a 4-core host machine.

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Section: Introductionmentioning

confidence: 99%

Parallelization of IBM mambo system simulator in functional modes

Wang

Shen

2008

SIGOPS Oper. Syst. Rev.

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“…Software is very flexible but also comes with inherent overheads [7]. On the contrary Hardware Transactional Memory systems are fast for transactions that fit into the restricted hardware [8], [9], [10]. Further, hybrid approaches, combining hardware and software to accelerate execution and lift the limits of the hardware have been researched [11], [12], [13], [14].…”

Section: Background and Related Workmentioning

confidence: 99%

What Scientific Applications can Benefit from Hardware Transactional Memory?

Schindewolf¹,

Bihari²,

Gyllenhaal³

et al. 2012

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Abstract-Achieving efficient and correct synchronization of multiple threads is a difficult and error-prone task at small scale and, as we march towards extreme scale computing, will be even more challenging when the resulting application is supposed to utilize millions of cores efficiently. Transactional Memory (TM) is a promising technique to ease the burden on the programmer, but only recently has become available on commercial hardware in the new Blue Gene/Q system and hence the real benefit for realistic applications has not been studied, yet.This paper presents the first performance results of TM embedded into OpenMP on a prototype system of BG/Q and characterizes code properties that will likely lead to benefits when augmented with TM primitives. We first, study the influence of thread count, environment variables and memory layout on TM performance and identify code properties that will yield performance gains with TM. Second, we evaluate the combination of OpenMP with multiple synchronization primitives on top of MPI to determine suitable task to thread ratios per node. Finally, we condense our findings into a set of best practices. These are applied to a Monte Carlo Benchmark and a Smoothed Particle Hydrodynamics method. In both cases an optimized TM version, executed with 64 threads on one node, outperforms a simple TM implementation. MCB with optimized TM yields a speedup of 27.45 over baseline.

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“…It avoids memory conflicts by monitoring a transaction, a set of speculative operations in a defined code section. Numerous TM algorithms have been proposed [15][16][17][18][19]. BlueGene/Q is the first commercially available platform that implements TM in the hardware using multi-versioned L2 cache.…”

Section: Hardware Transactional Memory On Bluegene/qmentioning

confidence: 99%

Performance Characteristics of Hardware Transactional Memory for Molecular Dynamics Application on BlueGene/Q: Toward Efficient Multithreading Strategies for Large-Scale Scientific Applications

Kunaseth

Kalia

Nakano

et al. 2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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Abstract-Wehave investigated the performance characteristics of hardware transactional memory (HTM) on the BlueGene/Q computer in comparison with conventional concurrency control mechanisms, using a molecular dynamics application as an example. Benchmark tests, along with overhead-cost and scalability analysis, quantify relative performance advantages of HTM over other mechanisms. We found that the bookkeeping cost of HTM is high but that the rollback cost is low. We propose transaction fusion and spatially-compact scheduling techniques to reduce the overhead of HTM with minimal programming. A strong scalability benchmark shows that the fused HTM has the shortest runtime among various concurrency control mechanisms without extra memory. Based on the performance characterization, we derive a decision tree in the concurrencycontrol design space for multithreading application.

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ATLAS: A Chip-Multiprocessor with Transactional Memory Support

Cited by 28 publications

References 22 publications

Parallelization of IBM mambo system simulator in functional modes

Parallelization of IBM mambo system simulator in functional modes

What Scientific Applications can Benefit from Hardware Transactional Memory?

Performance Characteristics of Hardware Transactional Memory for Molecular Dynamics Application on BlueGene/Q: Toward Efficient Multithreading Strategies for Large-Scale Scientific Applications

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