Atomistic modelling for boron diffusion profile in silicon posterior to germanium pre-amorphization

Kim, Joong-sik; Won, Taeyoung

doi:10.1016/j.mee.2007.01.254

Cited by 6 publications

(2 citation statements)

References 3 publications

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“…Referring to Figure 8, we see that the proposed device has a maximum impact ionization as low as 2 44 × 10 16 cm −3 s −1 at V DS = 70 V, whereas the conventional one has a value of 6 69 × 10 19 cm −3 s −1 at the same condition, which implies that the proposed LDMOS reduces the carrier generation near the drain at high V GS and V DS to ensure high on-state breakdown voltage. [9][10][11][12][13] Figure 9 shows the simulated device structure and the impact ionization rates at V DS = 30, 50, and 70 V. The high impact ionization spot moves from the gate to the drain due to the high level of current density. As illustrated in Figure 9, the proposed LDMOS reduces the carrier generation near the drain at high V GS and V DS to ensure high on-state breakdown voltage.…”

Section: Resultsmentioning

confidence: 99%

Impact of Drift Gap, N-Layer, and Deep N+ Sinker on Breakdown Voltage and Saturation Current of Lateral Double-Diffused Metal Oxide Semiconductor Transistor

Sung

Won²

2011

J. Nanosci. Nanotech.

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In this paper, we discuss on the optimal design of a High-Side n-channel Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET) whose breakdown voltage is over 100 V with 0.35 microm Bipolar-CMOS-DMOS (BCD) process. The proposed nLDMOSFET has been fabricated and tested in order to confirm the features of a deep N+ sinker and a gap of between the drift region (DEEP N-WELL) and the center of the source. The surface is implanted by the N-layer for high breakdown voltage and simultaneously the low specific on-resistance. The computer simulation of the proposed High-Side LDMOS exhibits BVdss of 115 V and Ron,sp of as low as 2.20 m ohms cm2, which is consistent with the experimental results.

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Section: Resultsmentioning

confidence: 99%

Impact of Drift Gap, N-Layer, and Deep N+ Sinker on Breakdown Voltage and Saturation Current of Lateral Double-Diffused Metal Oxide Semiconductor Transistor

Sung

Won²

2011

J. Nanosci. Nanotech.

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“…After the implant process, we implement the annealing process using our KMC code [6,7]. In the KMC approach, a physical system which consists of many possible events evolves as a series of independent events.…”

Section: Thermal Annealing Simulationmentioning

confidence: 99%

Investigation of boron diffusion after pre-amorphization implant with kinetic Monte Carlo approach

2008

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In this paper, we report our theoretical investigation on boron diffusion in silicon posterior to PAI (preamorphization implant) process in an effort to understand the physical mechanism for forming a shallow and abrupt junction. We performed numerical calculation for examining the characteristics of silicon atoms as a candidate for PAI species. Our KMC (Kinetic Monte Carlo) simulation revealed that PAI process helps to get a shallower junction than the case of PAI-free boron implantation and that Si-PAI process produces more amount of interstitial and vacancy which results in the reduction of so-called boron transient enhanced diffusion (TED). In addition, we made a comparison between Si-PAI and Ge-PAI in terms of the generation dynamics of defects and the effect on the subsequent diffusion of boron. Our KMC study on the interstitial distribution revealed that Si-PAI produces more interstitials than Ge-PAI whilst Ge-PAI help interstitials move further up toward the surface than Si-PAI during the subsequent annealing process.

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Kinetic Monte Carlo study on boron diffusion posterior to pre-amorphization implant process

Park

Kim

Won

2009

Microelectronic Engineering

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Atomistic modelling for boron diffusion profile in silicon posterior to germanium pre-amorphization

Cited by 6 publications

References 3 publications

Impact of Drift Gap, <I>N</I>-Layer, and Deep N<SUP>+</SUP> Sinker on Breakdown Voltage and Saturation Current of Lateral Double-Diffused Metal Oxide Semiconductor Transistor

Impact of Drift Gap, <I>N</I>-Layer, and Deep N<SUP>+</SUP> Sinker on Breakdown Voltage and Saturation Current of Lateral Double-Diffused Metal Oxide Semiconductor Transistor

Investigation of boron diffusion after pre-amorphization implant with kinetic Monte Carlo approach

Kinetic Monte Carlo study on boron diffusion posterior to pre-amorphization implant process

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