2003
DOI: 10.1143/jjap.42.6390
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Au Bump Interconnection in 20 µm Pitch on 3D Chip Stacking Technology

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Cited by 49 publications
(21 citation statements)
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“…Usually, microbumps and solder-bumps are used for flip-chip bonding of chip-to-substrate interconnects. [2][3][4] When using solder-bumps for interconnects, the bump shape is affected by the reflow process, and decreasing the bump pitch is not easy. On the other hand, it is easy to attain a high-density pad pitch of microbumps, though obtaining bump arrays with a uniform bump height is essential.…”
Section: Introductionmentioning
confidence: 99%
“…Usually, microbumps and solder-bumps are used for flip-chip bonding of chip-to-substrate interconnects. [2][3][4] When using solder-bumps for interconnects, the bump shape is affected by the reflow process, and decreasing the bump pitch is not easy. On the other hand, it is easy to attain a high-density pad pitch of microbumps, though obtaining bump arrays with a uniform bump height is essential.…”
Section: Introductionmentioning
confidence: 99%
“…In recent years, the bump size for flip-chip bonding between a silicon die and a package has reached a value of the order of 10 µm [1,2,3,4]. With the downsizing of the interconnect bumps for flip-chip bonding, mechanical issues such as stress concentration in a bump due to thermal mismatch after bonding, or misalignment among bump junctions due to a limited alignment accuracy are becoming more serious.…”
Section: Introductionmentioning
confidence: 99%
“…4 Many researchers have investigated this method. 5,6 However, fine-pitch arrays of bumps of the order of micrometers in height and width are not easy to fabricate. Moreover, insufficient accuracy in alignment in the chip-to-substrate bonding is becoming a serious problem in dealing with finer bumps.…”
mentioning
confidence: 99%