The national project of “Ultra High-Density Electronic System Integration” was initiated in 1999. This is the first project to focus on a niche area between electronic devices and systems. It aims to develop technologies for overcoming the problems in terms of performance of electronic systems. Three-dimensional (3D) LSI chip stacking, optoelectronics hybrid integration, and optimum circuit design are the technology categories. For the 3D stacking technology, a chip-based stacking technology is under extensive development that includes wafer preparation for chip stacking, wafer thinning, chip stacking, and inspection and testing. In this paper, the current development status of the 3D stacking technology, called V-STACK technology, is introduced.

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Mechanical effects of copper through-vias formed in silicon dies in a three dimensional module, in which four baredies with copper through-vias are vertically stacked and electrically connected through the copper-vias and metal bumps, were numerically and experimentally studied. To examine the mechanical effects caused by the existence of the copper through-vias in a rigid silicon-chip, a series of stress analyses, related simple mechanical tests, and reliability tests were carried out. All these results show that the copper through-via has unique effects on the stress distribution caused by thermal mismatch and on the interconnection reliability in the 3D die-stacked module. In particular, it was found that the developed micro copper through-via is reliable because the stress distribution due to thermal load is close to the hydrostatic pressure condition, and enhances chip-to-chip interconnection reliability because the copper-via restrains the plastic deformation of a gold bump during temperature

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The advanced 3D stacking technologies are discussed in this paper. They are the microbumping in 20µm pitch, the basic processes of the advanced bonding processes for the high precision and the reliable interconnections, the novel technologies to encapsulate the layered microthin gaps less than 10µm, and the non-destructive inspection. These technologies are confirmed to realize the 3D stacked LSI structure, and it will be expanded to the advanced system packaging technologies in the near future. IntroductionNowadays, the demand for the high-density electronics component is quite general for the consumer information equipment. The new packaging technologies are required to break through the limitation of the conventional package performance [1]. The developed 3D LSI has the through-hole copper electrodes in the Si devices, which are formed by the reactive ion etching (RIE) process in 20µm pitch for the vertical wiring retributions. The substantial technologies for the 3D stacked LSI are the hyperfine interconnections of the microbumps on the through-hole electrodes and the encapsulation of the narrow gaps through the layered devices. The established results for each essential technology are introduced respectively as following.