The national project of “Ultra High-Density Electronic System Integration” was initiated in 1999. This is the first project to focus on a niche area between electronic devices and systems. It aims to develop technologies for overcoming the problems in terms of performance of electronic systems. Three-dimensional (3D) LSI chip stacking, optoelectronics hybrid integration, and optimum circuit design are the technology categories. For the 3D stacking technology, a chip-based stacking technology is under extensive development that includes wafer preparation for chip stacking, wafer thinning, chip stacking, and inspection and testing. In this paper, the current development status of the 3D stacking technology, called V-STACK technology, is introduced.

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Mechanical effects of copper through-vias formed in silicon dies in a three dimensional module, in which four baredies with copper through-vias are vertically stacked and electrically connected through the copper-vias and metal bumps, were numerically and experimentally studied. To examine the mechanical effects caused by the existence of the copper through-vias in a rigid silicon-chip, a series of stress analyses, related simple mechanical tests, and reliability tests were carried out. All these results show that the copper through-via has unique effects on the stress distribution caused by thermal mismatch and on the interconnection reliability in the 3D die-stacked module. In particular, it was found that the developed micro copper through-via is reliable because the stress distribution due to thermal load is close to the hydrostatic pressure condition, and enhances chip-to-chip interconnection reliability because the copper-via restrains the plastic deformation of a gold bump during temperature

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