Auto-Calibrating TDC for a SoC-FPGA Data Acquisition System

Abstract

In this work, an FPGA-based plain delay line TDC is presented, together with a theoretical model on its timing properties. The TDC features an automated calibration system implemented in the on-chip processor of a SoC-FPGA, uses a low amount of FPGA resources and is therefore suitable for applications requiring a high number of channels such as Time-of-Flight Positron Emission Tomography. We first investigated the importance of calibration and validated the theoretical model on the TDC timing properties. Finally, the device has been embodied into a two channel Positron Emission Tomography acquisition system and tested. We found the calibration essential to obtain a good time resolution (38 ps FWHM in comparison with a 78 ps FWHM obtained with the uncalibrated device). The model we developed is able to predict the TDC timing properties. They are shown to be related to the fundamental parameters of the used FPGA technology. In particular, the best achievable time resolution of this specific architecture (plain tapped delay line on FPGA) is set to about 30 ps by the sum of the setup and hold times of the registers in the FPGA. The timing resolution of the twochannel setup is about 118 ps. Index Terms-FPGA, positron emission tomography, scintillators, time-of-flight, time-to-digital converters. I. INTRODUCTION IGH resolution instruments for measuring temporal intervals find various applications both in the industry and in research. Examples are optical spectroscopy, mass Manuscript received April 4, 2018. The research leading to these results has received partial funding from the European Union Seventh Framework Programme (FP7/2007-2013) under grant agreement n° 602621-Trimage.

Design and Evaluation of an FPGA-ADC Prototype for the PET Detector Based on LYSO Crystals and SiPM Arrays

“…For the time measurement, a carry chain FPGA-TDC with an effective bin size of around 20 ps is employed. Previous research indicated that the resolution of this type TDC could be better than 60 ps FWHM [37], which is good enough for the TOF-PET application. For the energy measurement, the analogue signals from E, Ex and Ey are shaped to a Quasi Gaussian pulse by a CR-RC 3 filter and then fed into the FPGA-ADCs.…”

“…Fortunately, researches in recent years succeed in integrating high-resolution time-digital converters into the Field Programmable Gate Array device (FPGA-TDC) which makes the time measurement much simpler [20][21][22][23]. Nevertheless, the energy measurement is commonly based on a commercial highspeed analog-digital converter (ADC) chip to digitalize the analogue signals, which certainly leads to high system power consumption and cost [24].…”

Design and Detector Performance of the PET Component of the TRIMAGE PET/MR/EEG Scanner

“…Each data packet is decoded by the FPGA and its TDC payload is calibrated using a calibration map that is loaded on-chip at boot time. For this purpose, we use a quantile-wise time calibration [24], [25]. All the data packets of a single event are referred to as a frame and are stored in the FPGA for on-line processing.…”