Auto-vectorization of interleaved data for SIMD

Abstract

Most implementations of the Single Instruction Multiple Data (SIMD) model available today require that data elements be packed in vector registers. Operations on disjoint vector elements are not supported directly and require explicit data reorganization manipulations. Computations on non-contiguous and especially interleaved data appear in important applications, which can greatly benefit from SIMD instructions once the data is reorganized properly. Vectorizing such computations efficiently is therefore an ambitious challenge for both programmers and vectorizing compilers. We demonstrate an automatic compilation scheme that supports effective vectorization in the presence of interleaved data with constant strides that are powers of 2, facilitating data reorganization. We demonstrate how our vectorization scheme applies to dominant SIMD architectures, and present experimental results on a wide range of key kernels, showing speedups in execution time up to 3.7 for interleaving levels (stride) as high as 8.

Compiling C/C++ SIMD Extensions for Function and Loop Vectorizaion on Multicore-SIMD Processors

“…There has been a rich body of compiler research and development on exploiting SIMD parallelism for modern CPU and GPU cores with rich and powerful SIMD hardware support [1,2,3,4,5,7,10,14] through compiler auto-vectorization. However, the modern SIMD architecture poses new constraints such as data alignment, masking for control flow, non-unit stride access to memory, fixedlength nature of SIMD vectors, even though, there has been a huge effort being made in the past decade to address these challenges to certain extent [1,5,7,13,14], often times, the compiler automatic vectorization would still fail to vectorize application programs or fail to generate optimized SIMD code due to various reasons such as compile-time unknown loop trip count, memory access stride and patterns, alignment and control flow complexity.…”

“…However, the modern SIMD architecture poses new constraints such as data alignment, masking for control flow, non-unit stride access to memory, fixedlength nature of SIMD vectors, even though, there has been a huge effort being made in the past decade to address these challenges to certain extent [1,5,7,13,14], often times, the compiler automatic vectorization would still fail to vectorize application programs or fail to generate optimized SIMD code due to various reasons such as compile-time unknown loop trip count, memory access stride and patterns, alignment and control flow complexity. When that happens, the programmer would have to perform low-level SIMD intrinsic programming or write inline ASM code in order to utilize SIMD hardware resources effectively [6].…”

“…To make efficient use of the underlying SIMD hardware, utilizing its wide vector registers and SIMD instructions --Single Instructions operating on Multiple Data elements packed in wide registers such as AltiVec [2], SSE, AVX and MIC, SIMD vectorization plays a key role of converting plain scalar C/C++ code into SIMD code that operating on vectors of data each holding one or more elements [1,2,5,14].…”

High-order stencil computations on multicore clusters

“…Most modern computing platforms have incorporated single-instruction multiple-data (SIMD) extensions into their processors [22] to exploit the natural parallelism of applications if the data can be SIMDized (i.e., if a single instruction can simultaneously operate on a vector of consecutive data). On Cell BE, each vector contains four floating-point numbers that are operated concurrently, and thus the ideal speedup is 4.…”

Data layout optimization for multi-valued containers in OpenCL

“…It is particularly severe for SIMD units when they need to collect data from multiple strided addresses for parallel processing. Data permutations improving the data layout are an active area of research [15,13]. Intel Array Building Blocks [6] also perform dynamic layout transformations of user data for better parallel processing speed.…”