High-order stencil computations on multicore clusters

Abstract

Stencil computation (SC) is of critical importance

Collective Memory Transfers for Multi-Core Chips

“…We believe that the kinds of algorithms that are the largest drivers for improved computational performance are in fact these kinds of SPMD kernels that are seen in image processing, face recognition, machine learning, fluid dynamics, linear algebra, kinetics simulation, and numerous others. Even though mappings alternative to row-or column-major can produce a more favorable memory access stream for some applications without CMS [27,55,32,67], the baseline still cannot outperform CMS even with complex data layout transformations. CMS will also benefit communication-avoiding optimizations which tradeoff reduced memory traffic for redundant computation [51,28,18].…”

“…To illustrate the benefits of CMS, we focus on stencil algorithms because of their broad applicability, the memory bandwidth sensitivity of their kernels [36,18,12,1], and their ubiquitous usage [55]. In particular, stencil algorithms constitute a large fraction of consumer, embedded, HPC and scientific applications in such diverse areas as image processing, seismic imaging [46], heat diffusion, electromagnetics, fluid dynamics, and climate modeling [51,52,78,56].…”

“…In the common case that a processor's tile consists of non-contiguous memory addresses [27,55,32,67], a potentially large number of DMA calls is required, which in turn require deep transaction queues in each DMA engine [40]. As an example, to transfer a tile in a 64-core system from a 2048×2048 HTA without architectural support for strided memory access, similar to the STI Cell [62], each processor requires 256 separate DMA transfers.…”

“…Past work has repeatedly reported that a wide variety of applications are constrained by memory bandwidth [65,28,64,59,36,18,46,12,32,55]. In those cases, while local and last-level caches can eliminate DRAM accesses during the computation phase of a loop, data is still retrieved from main memory when loading new and storing old HTAs, which is the focus of CMS.…”

“…Memory bandwidth is not scaling rapidly enough to satisfy the increasing number of processors, making the performance of a wide variety of applications constrained by memory bandwidth [70,66,59,12,32,18,19,28,30,2,55]. In fact, current projections state that chip pins increase by 10% every year whereas on-chip processors double every 18 months [59].…”