Automated fixed-point precision optimization

Özdil, Ömer; Ispir, Mehmet; Onat, Emrah; Yıldırım, Alper

doi:10.1109/siu.2012.6204532

Cited by 3 publications

(3 citation statements)

References 3 publications

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“…The word length optimization in HLS based approach is under research from last two decades. Several approaches [8][9] [10][11] [12] were evolved and further optimization is under research. Existing optimization algorithms established methods for floating point to fixed point mapping under given constraints.…”

Section: (2)mentioning

confidence: 99%

“…The paper given at [17], depicts specification of arithmetic circuits and explains the techniques for verification and bit optimization in arithmetic circuit designs. An algorithm given at [10] minimizes the hardware resources of fixed-point operations for a given accuracy constraints. The work uses weighted search algorithm, which can minimize the hardware resources for a specific FPGA by using weights.…”

Section: (2)mentioning

confidence: 99%

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Multiple Word Length based low power digital base band receiver

Manga¹,

Latha²

2014

IOSRJVSP

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Section: (2)mentioning

confidence: 99%

Section: (2)mentioning

confidence: 99%

Multiple Word Length based low power digital base band receiver

Manga¹,

Latha²

2014

IOSRJVSP

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“…An algorithm given at [10] minimizes the hardware resources of fixed-point operations for a given accuracy constraints. The work uses weighted search algorithm, which can minimize the hardware resources for a specific FPGA by using weights.…”

Section: Fig 1: Scope Of Power Optimization At Variousmentioning

confidence: 99%

Low Power Blind Adaptive Equalizer with Word Length Optimization Algorithm

Manga¹,

Latha²

2014

IJCA

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Low power VLSI is a promising area for developing advanced wireless communication systems. The optimum word length selection for each signal in algorithm is crucial for low power design. This paper proposes a scheme for Word Length Optimization (WLO) using system level parameters such as dynamic range and SNR. The Blind Adaptive Equalizer for channel equalization is optimized with the proposed technique for fixed point implementation in VHDL. Simulation is carried out in MATLAB and also VHDL. Considering IEEE 802.16 wireless broadband network and DSL cable modem standards, the results are validated for Energy per Symbol to Noise density (Es/No) values 8 dB and 12 dB. Power saving up to 34% is observed for Xilinx's Virtex-6 FPGAs, in comparison with conventional implementation. The result shows promising direction of optimization with good scope of automation for low power wireless applications. The suitability of adopted WLO scheme in the context of High Level Synthesis (HLS) is discussed. General TermsLow power VLSI, communication system design, Register Transfer Level (RTL), Algorithm to RTL et. al.

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Power optimized high level synthesis of Multiply-and-Accumulate (MAC) based digital filter architectures under SNR constraints

Manga

Latha

2014

International Conference on Information Communication and Embedded Systems (ICICES2014)

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Automated fixed-point precision optimization

Cited by 3 publications

References 3 publications

Multiple Word Length based low power digital base band receiver

Multiple Word Length based low power digital base band receiver

Low Power Blind Adaptive Equalizer with Word Length Optimization Algorithm

Power optimized high level synthesis of Multiply-and-Accumulate (MAC) based digital filter architectures under SNR constraints

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