Automated formal synthesis of Wallace Tree multipliers

Abstract

In this paper, we present a formal synthesis methodology that is capable of performing correct synthesis at almost all levels of abstraction and can be adapted to be used for most of the combinational digital circuits irrespective of their size and complexity. The proposed methodology calls for proving the correctness-preserving characteristic for the transformations that are required in the synthesis of a particular digital circuit in a higher-order-logic theorem prover. These correctnesspreserving transformation proofs can then be used to automatically verify the correctness of the corresponding synthesis process within the theorem prover in an automated way. For illustration purposes, we present the construction of an automated formal synthesis tool for Wallace Tree multipliers based on our methodology.

Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

“…It is discussed that multiplication consists of three major steps: 1) encoding and generating partial products; 2) reducing the partial products by reduction schemes (e.g., Wallace tree [33], [34]) to final two rows; and 3) adding the remaining two rows of partial products by using a carry propagate adder to obtain the final product. In this proposed design, the focus is on the first two-step to reduce hardware cost, delay, and power consumption of proposed multiplier [35].…”

CMOS implementation of a new high speed 5-2 compressor for parallel accumulations

“…A 5-2 compressor gets five primary inputs a 1 , a 2 , a 3 , a 4 , a 5 and C in1 , C in2 as carry-input bits from a neighboring one lower significant cell with weights of one and generates Sum and Carry outputs with weights of one and two and generates C out1 and C out2 outputs as carry-out bits with weights of two. …”

“…Also, for C in1 ⊕ C in2 = 0, Sum output is equal to the XOR of a 1 , a 2 , a 3 , a 4 , a 5 and for C in1 ⊕ C in2 = 1, it is equal to the XNOR of these inputs as:…”

“…In multiplication higher than 16 bits, the most significant delay belongs to the summation stage. By use of carry save adders (CSA) in Wallace and Dadda trees [4], the delay of this stage is reduced. A major intention of CSA arrangements is obtained by compressor structures [5].…”

A new ultra high speed 7-2 compressor with a new structure

“…In multiplications higher than 16 bits the most significant part of total delay belongs to the second stage which makes the worst case delay, consumes the main part of power, and occupies the high fraction of silicon area. A high performance method to lower the latency of the accumulation stage is to use carry save adders (CSA) in Wallace and Dadda trees [5]. Another method is called carry look ahead adder (CLA) which is used in many articles [6].…”