Automated generation of DSP program development tools using a machine description formalism

Fauth, A.; Knoll, Alois

doi:10.1109/icassp.1993.319154

Cited by 36 publications

(29 citation statements)

References 5 publications

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“…nML has been used by code generators CBC [13] and CHESS [14], and instruction set simulators Sigh=Sim [15] and CHECKERS. Currently, the CHESS=CHECKERS environment is used for automatic and efficient software compilation and instruction set simulation [16].…”

Section: Behavioural Adlsmentioning

confidence: 99%

Processor Description Languages

Mishra¹,

Dutt²

2008

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Embedded systems present a tremendous opportunity to customise designs by exploiting the application behaviour. Shrinking time-to-market, coupled with short product lifetimes, create a critical need for rapid exploration and evaluation of candidate architectures. Architecture description languages (ADL) enable exploration of programmable architectures for a given set of application programs under various design constraints such as area, power and performance. The ADL is used to specify programmable embedded systems, including processor, coprocessor and memory architectures. The ADL specification is used to generate a variety of software tools and models facilitating exploration and validation of candidate architectures. The paper surveys the existing ADLs in terms of (a) the inherent features of the languages and (b) the methodologies they support to enable simulation, compilation, synthesis, test generation and validation of programmable embedded systems. It concludes with a discussion of the relative merits and demerits of the existing ADLs and expected features of future ADLs.

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Section: Behavioural Adlsmentioning

confidence: 99%

Processor Description Languages

Mishra¹,

Dutt²

2008

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“…The process of building this model is detailed in [10,12]. The machine model, along with 'the datapath constraints and machine-independent transformation rules are given as input to the generic (parameterized) code generator.…”

Section: Retargetingmentioning

confidence: 99%

“…Nevertheless, similar tools can be used at the technical level. In the CBC environment, all legal patterns are generated by the nML front-end [9] and stored as a set of match-replace pairs (see Fig. 5 for an example).…”

Section: Matching On Treesmentioning

confidence: 99%

“…When retargeting the compiler, the nML analyzer examines the instruction set and the memory description of the target processor and builds a machine model, i.e. a representation of the capabilities and constraints of the machine.The process of building this model is detailed in [10,12]. The machine model, along with 'the datapath constraints and machine-independent transformation rules are given as input to the generic (parameterized) code generator.…”

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confidence: 99%

“…The transformation rules specify, for example, how to perform a 32-bit addition on a 16-bit machine. The phases of code generation and the construction of the generic compiler are outlined in [9,11]. …”

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confidence: 99%

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Global code selection for directed acyclic graphs

Fauth

Hommel

Knoll

et al. 1994

Lecture Notes in Computer Science

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Abstract. We describe a novel technique for code selection based on data-flow graphs, which arise naturally in the domain of digital signal processing. Code selection is the optimized mapping of abstract operations to partial machine instructions. The presented method performs an important task within the retargetable microcode generator CBC, which was designed to cope with the requirements arising in the context of custom digital signal processor (DSP) programming. The algorithm exploits a graph representation in which control-flow is modeled by scopes. IntroductionIn the domain of medium-throughput digital signal processing, micro-programmable processor cores are frequently chosen for system realization. By adding dedicated hardware (accelerator paths), these cores are tailored to the needs of new applications. Optimized processor modules can be reused, which is a major benefit compared to high-level synthesis [28] where a completely new design is developed for each application. Because of the application-specific add-ons and the rather short lifetimes of a specific design, there is a need for retargetable software development tools, especially code-generators. OverviewIn the next section we will shortly discuss several related approaches to code generation and point out some differences of our system. Section 3 introduces the overall architecture and functionality of the CBC code generator. Section 4 explains the code selection task and the basic techniques used. In section 5 our algorithm is presented. We conclude the paper with experimental results. Points of major differences between our code selection approach and similar tasks in "classic" code generation (CG) are: -Complexity of datapaths. CBC has to deal with highly specialized and optimized datapaths. The hardware units make the efficient execution of frequently used operation sequences possible. Operation patterns for the functional units of these datapaths are much more complex than for standard microprocessors.-Type-handling. DSP algorithms may employ a large variety of different word lengths and numerical types. The hardware operators are restricted to fixed word lengths. A correct mapping must always be found. In most CG work this topic is neglected because language definitions (and hence the compilers) are restricted to "implementation-dependent" types. -Evaluation order. Approaches like [6,7] dealing with code selection assume a fixed evaluation order, which is usually derived from the imperative source code. There is no explicit scheduling phase included in the back-ends. Commonly, register allocation is performed during code selection. Most of the time this is done by graph coloring [4] or "on-the-fly".Parallelism of functional blocks. Most DSP architectures contain several functional units that work in parallel. Therefore, the final code cannot be emitted during or immediately after the code selection phase because partial instructions must be "compacted" into complete instructions at a later stage of compilation exploiting the possible para...

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