Automated Hardware IP Generation for Digital Signal Processing Applications

Hourani, Ramsey; Kim, Youngsoo; Ocloo, Senanu; Alexander, W.E.

doi:10.1109/acssc.2006.354936

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…Linear-phase FIR filters exhibit symmetry properties in the filter coefficients which permit designers to use a folded architecture for a reduced hardware implementation. The folded design shares the multipliers between pairs of input signals which effectively reduces the hardware complexity by approximately 50% [29]. This is observed by the following difference equation for a 9-tap, linear-phase FIR filter.…”

Section: Expanding the Fir Filter Design Spacementioning

confidence: 87%

Automated Design Space Exploration for DSP Applications

Hourani

Jenkal

Davis

et al. 2008

J Sign Process Syst Sign Image Video Technol

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We present a performance analysis framework that efficiently generates and analyzes hardware designs for computationally intensive signal processing applications. Our framework synthesizes designs from a high level of abstraction into well-constructed and recognizable hardware structures that perform well in terms of area, throughput and power dissipation. Cost functions provided by our framework allow the user to reduce the design space to a set of efficient hardware implementations that meet performance constraints. We utilize our framework to estimate hardware performance using a set of pre-synthesized mathematical cores which expedites the synthesis process by approximately 14 fold. This reduces the architectural generation and hardware synthesis process from days to several hours for complex designs. Our work aims at performing hardware optimizations at the architectural and arithmetic levels, relieving the user from manually describing the designs at the register transfer level and iteratively varying the hardware structures. We illustrate the efficiency and accuracy of our framework by generating finite impulse response filter structures used in several signal processing applications such as adaptive equalizers and quadrature mirror filters. The results show that hardware filter structures generated by our framework can achieve, on average, a 3 fold increase in power efficiency when compared to manually constructed designs.

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Section: Expanding the Fir Filter Design Spacementioning

confidence: 87%

Automated Design Space Exploration for DSP Applications

Hourani

Jenkal

Davis

et al. 2008

J Sign Process Syst Sign Image Video Technol

Self Cite

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“…FIR filters are unit applicable for improving the performance of the DWT hardware design [2]. A range of approaches for high speed implementation of FIR filters are conferred [3][4][5][6][7][8][9][10]. Novel area-efficient architectures of FIR filters are proposed by Benkrid and Benkrid [11].…”

Section: Introductionmentioning

confidence: 99%

A Novel Vlsi Architecture of High Speed 1d Discrete Wavelet Transform

Gupta¹,

Lenka²

2015

IJEEE

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This paper describes an efficient implementation for a multi-level convolution based 1-D DWT hardware architecture for use in FPGAs. The proposed architecture combines some hardware optimization techniques to develop a novel DWT architecture that has high performance and is suitable for portable and high speed devices. The first step towards the hardware implementation of the DWT algorithm was to choose the type of FIR filter block. Firstly we design the high speed linear phase FIR filter using pipelined and parallel arithmetic methods. This proposed filter employs efficiently distributed D-latches and multipliers. Furthermore this filter is used in the proposed DWT architecture. Thus, the new VLSI architecture based on combining of fast FIR filters for reducing the critical path delay and data interleaving technique for lower chip area. We synthesized the final design using Xilinx 9.1i ISE tool. We illustrate that a DWT design using a pipelined linear phase FIR filter coupled with data-interleaving gives the best combination of the performance metrics when compared to other DWT structures.

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