Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems

Abstract

Abstract-This paper presents a systematic approach for microarchitectural exploration in pipelined asynchronous systems, with the goal of achieving a specified throughput target while minimizing a given cost function (based on energy, area, etc.). The method includes a general framework that (i) allows for a rich extensible set of microarchitectural transformations for improving throughput; and (ii) can handle a variety of cost functions, such as area, energy, Eτ 2 and the energy-area product. In general, the space of transformations that can be applied to a given circuit is potentially infinite because an arbitrarily long sequence of transformations may be applicable. To compound the challenge, the value of the given cost function can change non-monotonically as successive transformations are applied (e.g., some transformations increase area, while others decrease area), thereby making it difficult to apply a typical branch-and-bound approach to prune the search space. Our method employs simple but effective heuristic search strategies (including greedy, lookahead, and breadth-first). A key contribution is to identify commutativity of certain transformations, thereby pruning the design space significantly. The approach was automated and applied to a number of examples. Various throughput targets were assumed: from 50% to 20x throughput improvement. In each example, the approach was successful in meeting the throughput target.

Asynchronous Design—Part 2: Systems and Methodologies

“…Other approaches target the specialized problem of performance analysis of pipelined asynchronous systems. 19,20 …”

“…FIFO insertion), splitting and coalescing of pipeline stages, loop unrolling and automatic pipelining. 19,20 An automated tool flow, called Proteus, 20 was developed at Fulcrum Microsystems for highperformance asynchronous ASICs, incorporating a number of these optimizations, as well as a highlevel CSPbased HDL (CAST) and RTL translator (CAST2RTL). The tool was recently migrated to Intel, and used to design its FM5000/6000 series Ethernet switch chips.…”