Automated synthesis for testability

Brglez, Franc; Bryan, D.; Calhoun, J.; Kedem, G.; Lisanke, R.

doi:10.1109/41.19078

Cited by 27 publications

(3 citation statements)

References 25 publications

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“…Inserting a new redundant wire means introducing a new gate, or swapping to a wider gate, capable of receiving the extra connection. ATPG engines are historically quite efficient to detect such redundancies [24]. Boolean rewiring is classically a greedy technique, where single rewiring operations are immediately accepted when positive gain is observed.…”

Section: Boolean Rewiring Revisited For Lutsmentioning

confidence: 99%

LUT-Based Optimization For ASIC Design Flow

Amarù

Possani

Testa

et al. 2021

2021 58th ACM/IEEE Design Automation Conference (DAC)

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Look-up Table (LUT) mapping and optimization is an important step in Field Programmable Gate Arrays (FPGAs) design. The effectiveness of LUT synthesis improved dramatically in the last decades, thanks to optimization and mapping innovations naturally tailored for FPGAs. In this paper, we develop a new LUT-based optimization flow that is tailored for the synthesis of Application-Specific Integrated Circuits (ASICs) rather than FPGAs. We enhance LUT mapping to consider the literal/AIG cost of LUT nodes. We extend traditional Boolean methods to simplify and re-shape LUT-networks, targeting the best AIG/mapped-network implementation, after decomposition. Intuitively, literal-driven LUT packing behaves as a powerful fanin-bound node elimination, unveiling higher-order Boolean simplification opportunities. We embed our proposed LUT-based optimization flow, area oriented, in a commercial synthesis tool. Using our methodology, we improve 12 of the best area results in the EPFL synthesis competition. Employed in a commercial EDA flow for ASICs, our LUT optimization reduces area by 1.80%, total negative slack by 0.39%, and switching power by 1.72%, after physical implementation, at 5% runtime cost.

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Section: Boolean Rewiring Revisited For Lutsmentioning

confidence: 99%

LUT-Based Optimization For ASIC Design Flow

Amarù

Possani

Testa

et al. 2021

2021 58th ACM/IEEE Design Automation Conference (DAC)

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“…3) Redundancy Removal and Rewiring: Redundancy removal is a common technique that uses automatic test pattern generators (ATPGs) to detect untestable stuck-at faults in an LN and modifies the network at the faulty net by setting it to a constant value [64], [65]. Rewiring improves on redundancy removal because it adds new connections in an LN to create redundancies that later can be removed.…”

Section: Example 12mentioning

confidence: 99%

Logic Synthesis for Established and Emerging Computing

et al. 2019

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| Logic synthesis is an enabling technology to realize integrated computing systems, and it entails solving computationally intractable problems through a plurality of heuristic techniques. A recent push toward further formalization of synthesis problems has shown to be very useful toward both attempting to solve some logic problems exactly-which is computationally possible for instances of limited size todayas well as creating new and more powerful heuristics based on problem decomposition. Moreover, technological advances including nanodevices, optical computing, and quantum and quantum cellular computing require new and specific synthesis flows to assess feasibility and scalability. This review highlights recent progress in logic synthesis and optimization, describing models, data structures, and algorithms, with specific emphasis on both design quality and emerging technologies. Example applications and results of novel techniques to established and emerging technologies are reported.

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“…Acomplete system for "easily" testable logic was reported in [27]. With regard to testability which is guaranteed complete in one sense or another, several papers have appeared.…”

Section: Synthesis For Testabilitymentioning

confidence: 99%