Logic Synthesis for Established and Emerging Computing

Testa, Eleonora; Soeken, Mathias; Amar, Luca Gaetano; Micheli, Giovanni De

doi:10.1109/jproc.2018.2869760

Cited by 31 publications

(16 citation statements)

References 109 publications

(150 reference statements)

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“…In [24], the authors present Majority-Inverter Graph (MIG), a new logic manipulation structure consisting of threeinput majority nodes and regular/inverted edges. Logic functions are represented by MIGs and further optimized using both algebraic and Boolean methods, summarized in [23], [24]. A selection of circuits from both IWLS'05 benchmarks and HDL arithmetic benchmarks were considered and synthesis results obtained with MIG optimization tool were compared to And-Inverter Graphs (AIG) optimized by ABC in terms of logical levels.…”

Section: Carry = Ab+bc In +Ac Inmentioning

confidence: 99%

“…Hence, a majority gate is a democratic gate and can be expressed in terms of Boolean AND/OR as M AJ(a, b, c) = a • b + b • c + a • c, where a, b, c are Boolean variables. Although majority logic was known since 1960, there has been a revival in using it for computation in many emerging nanotechnologies (spin waves, magnetic Quantum-Dot cellular automata, nano magnetic logic, Single Electron Tunneling [21]- [23]). Recent research [22]- [25] has confirmed that majority logic is to be preferred not only because a particular nanotechnology can realize it, but also because of its ability to implement arithmetic-intensive circuits with less gates.…”

Section: Introductionmentioning

confidence: 99%

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Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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To overcome the 'von Neumann bottleneck', methods to compute in memory are being researched in many emerging memory technologies including Resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistoraccessed ReRAM array during READ operation. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4•log(n)+6 for n-bit addition and is energy-efficient due to absence of sneak-currents in 1Transistor-1Resistor configuration.

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Section: Carry = Ab+bc In +Ac Inmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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“…This is one of the driving questions in logic synthesis, which is the process of optimizing logic representations under various criteria. Decades of research on this have considered various circuit models and produced many synthesis algorithms [1], [2], [3], [4]. In general, the problem of finding the smallest circuit for a given Boolean function is a computationally difficult task, and exact minimization is reasonably fast only for Boolean functions with a small number of inputs.…”

Section: Introductionmentioning

confidence: 99%

“…This notion of equivalence is called NPN (Negation-Permutation-Negation) equivalence [10], [11]. Formally, two Boolean functions are NPN equivalent if one can be obtained 1 Unlike the 3-input majority gate, a general 3-input gate can be asymmetric, thus in such a DAG representation, the ordering of the fan-in must be specified as well. Table I.…”

Section: Introductionmentioning

confidence: 99%

Three-Input Gates for Logic Synthesis

Marakkalage

Testa

Riener

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused primarily on graphs with 2-input nodes such as AND and OR gates, the recently proposed paradigm of Majority-Inverter Graphs instead uses the 3-input Majority gate as the node function. As this technique proved to be a success, it is natural to ask: Are there other 3-input gates better suited for logic synthesis? Motivated by this question, we investigate the relative advantages of 3-input gates as constituents of logic networks. We consider representative gates from each of the ten non-degenerate 3-input NPN classes and study how powerful they are at representing Boolean functions. Using SAT-based exact synthesis, we evaluate each 3-input gate using the minimum number of such gates (together with inverters) needed to synthesize all 4-input Boolean functions and a subset of frequent 5-input and 6-input Boolean functions. We show that the logic gate Dot(x, y, z) := x ⊕ (z ∨ x y) outperforms the rest in terms of expressive power. We further confirm this observation by showing that Dot-Inverter Graph representations are more than 14% smaller as compared to Majority-Inverter Graph representations of EPFL benchmarks.

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“…Beyond-CMOS research has been underway in the last decade to find an alternative device which is better than CMOS in its characteristics. This includes CMOS-like devices (tunnel FET, GaN TFET, Graphene ribbon pn junction, Ferroelectric FET) [4], quantum-dot cellular automata (QCA), nanomagnet logic, resistance-switching devices (Resistive RAM, Phase Change Memory, conductive bridge RAM), spin-based devices, and plasmonic-based devices [5]. Although some of these post-CMOS devices possessed valuable features like low-voltage operation and non-volatility, recent bench-marking efforts seem to suggest that none of these devices could outperform CMOS in the most critical aspects of computing (energy, latency and area) [4,6].…”

Section: Introductionmentioning

confidence: 99%

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Reuben

2020

JLPEA

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As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

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Logic Synthesis for Established and Emerging Computing

Cited by 31 publications

References 109 publications

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Three-Input Gates for Logic Synthesis

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

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