Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Reuben, John

doi:10.3390/jlpea10030028

Cited by 29 publications

(25 citation statements)

References 63 publications

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“…Fig. 1: In-memory implementation does not favor heterogeneity of logic primitives [26]. Arithmetic circuits are synthesized in terms of a particular logic primitive which can be implemented with minimal modifications to the conventional memory array.…”

Section: Carry = Ab+bc In +Ac Inmentioning

confidence: 99%

“…It is evident that majority logic could achieve 1-bit adder functionality with less logical depth (latency) than NAND/NOR. Furthermore, notice that k-levels of logic gets expanded to k + x cycles in memory (interconnections between logic levels contribute to x additional cycles, [26]). Therefore, for latency-optimized in-memory implementation, it is important to choose a logic primitive which minimizes k, the number of logic levels.…”

Section: Carry = Ab+bc In +Ac Inmentioning

confidence: 99%

“…11. The steps are 1) Majority at col. (1,9,26,33,42,49,58,65). In the above mapping, it must be noted that each bitwise majority operation is a READ operation and it must be followed by WRITE to be used as an input to the next logic level.…”

Section: B Mapping Of the Eight-bit Pp Adder To 1t-1r Arraymentioning

confidence: 99%

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Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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To overcome the 'von Neumann bottleneck', methods to compute in memory are being researched in many emerging memory technologies including Resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistoraccessed ReRAM array during READ operation. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4•log(n)+6 for n-bit addition and is energy-efficient due to absence of sneak-currents in 1Transistor-1Resistor configuration.

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Section: Carry = Ab+bc In +Ac Inmentioning

confidence: 99%

Section: Carry = Ab+bc In +Ac Inmentioning

confidence: 99%

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Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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“…These operations require the transfer of data elements between CPU and memory, thus limiting the overall computational speed. The phenomenon is known as the Von Neumann bottleneck [4,5]. A large number of studies have been conducted to address this problem.…”

Section: Introductionmentioning

confidence: 99%

An 8-bit Radix-4 Non-Volatile Parallel Multiplier

Zhu

Huang

et al. 2021

Electronics

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The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manchester carry chain are presented, which help to short the delay of the proposed multiplier. While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed. The proposed multiplier has an area of 785.2 μm2 with Generic Processing Design Kit 45 nm process. The simulation results show that the proposed multiplier structure has a low computing power at 161.19 μW and a short delay of 0.83 ns with 1.2 V supply voltage. Comparative analyses are performed to demonstrate the effectiveness of the proposed multiplier design. Compared with conventional booth multipliers, the proposed multiplier structure reduces the energy and delay by more than 70% and 19%, respectively.

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“…To overcome this latency hurdle, two paths were pursued-stronger logic primitives and parallel-prefix configurations. Majority logic primitive proved to be stronger than NAND/NOR/IMPLY primitives making in-memory addition fast [6]- [8]. To avoid rippling of carry, parallel-prefix adders were investigated.…”

Section: Introductionmentioning

confidence: 99%

Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles

Reuben

Fey

2021

2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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The movement of data between processing and memory units, often referred to as the 'von Neumann bottleneck' is the main reason for the degraded performance of contemporary computing systems. In an effort to overcome this bottleneck, methods to 'compute' at the location of data are being pursued in many emerging memories, including Resistive RAM (ReRAM). Although many prior works have pursued addition in memory, the latency of n-bit addition has not been judiciously optimized, resulting in O(n) or at best O(log(n)). Computing with three states can enable carry-free addition and result in a latency which is independent of operand width (O(1)). In this work, we propose a method to perform carry-free addition completely in memory (a storage array, a processing array and their peripheral circuitry). The proposed technique incurs a latency of 22 memory cycles, which outperforms other in-memory binary adders for n ≥ 32. This speed is achieved at the cost of increased peripheral hardware.

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Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Cited by 29 publications

References 63 publications

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

An 8-bit Radix-4 Non-Volatile Parallel Multiplier

Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles

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