Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles

Abstract

The movement of data between processing and memory units, often referred to as the 'von Neumann bottleneck' is the main reason for the degraded performance of contemporary computing systems. In an effort to overcome this bottleneck, methods to 'compute' at the location of data are being pursued in many emerging memories, including Resistive RAM (ReRAM). Although many prior works have pursued addition in memory, the latency of n-bit addition has not been judiciously optimized, resulting in O(n) or at best O(log(n)). Computing with three states can enable carry-free addition and result in a latency which is independent of operand width (O(1)). In this work, we propose a method to perform carry-free addition completely in memory (a storage array, a processing array and their peripheral circuitry). The proposed technique incurs a latency of 22 memory cycles, which outperforms other in-memory binary adders for n ≥ 32. This speed is achieved at the cost of increased peripheral hardware.

A Low-Power Ternary Adder Using Ferroelectric Tunnel Junctions

“…It is well known that ternary arithmetic (computing with three states instead of conventional two-states) can enable "carry-free" addition i.e., the rippling of carry from lower-significant bit can be avoided achieving O(1) latency for n-bit addition [9,10]. A ternary adder architecture was chosen and implemented using ReRAM technology in one of our earlier works [11].…”