Automatic Calibration Method of Channel Mismatches for Wideband TI-ADC System

Li, Jingyu; Pan, Jiameng; Zhang, Yue

doi:10.3390/electronics8010056

Cited by 22 publications

(14 citation statements)

References 32 publications

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“…Data acquisition systems have been widely used in instrument measurement, communication, aerospace and medical fields [1][2][3][4][5][6][7][8]. As the core component of a data acquisition system, an analog-to-digital converter (ADC) is the only way to achieve analog/digital conversion, the performance of the ADC has a direct impact on the performance of the data acquisition system [9].…”

Section: Introductionmentioning

confidence: 99%

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

Sun

Zhang

et al. 2022

Applied Sciences

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The performance of analog-to-digital converters (ADCs) has reached a bottleneck due to the limitations of the manufacturing process and testing environment. Time-interleaved ADC (TIADC) technology can increase the sampling rate without changing the resolution. However, channel mismatch severely degrades the dynamic performance of the TIADC system. For the channel mismatch problem of TIADC, most of the current solutions have preconditions, such as eliminating only some kind of error or increasing the complexity of the hardware. A few methods can estimate multiple errors without changing the hardware circuit. To improve the dynamic performance of the TIADC system, on the basis of an in-depth study of the channel mismatch error of TIADC, according to the system identification theory, an identification model is designed to characterize the frequency characteristics of TIADC. Using the system observation data, the transfer function parameters of the system are recursively estimated. By constructing and verifying the identification model of the TIADC system, and then through the frequency domain correction method, a digital compensation filter is established to complete the error correction of the system. The test results of the four-channel TIADC high-speed data acquisition system show that the actual input and output characteristics of the test system are consistent with the nature of the identification model. The four channels of the TIADC system are provided by four sub-channels of two AD9653 chips, and the highest sampling rate of a single channel is 125MSPS. For sinusoidal input signals from 20 MHz to 150 MHz, the sampling system can achieve a signal-to-noise ratio (SNR) above 56.8 dB and spurious free dynamic range (SFDR) above 69.7 dB. The dynamic performance of the sampling system is nearly equivalent to that of its sub-ADC; the feasibility of the model identification method and the effectiveness of error correction are verified in simulation and experiment.

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Section: Introductionmentioning

confidence: 99%

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

Sun

Zhang

et al. 2022

Applied Sciences

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“…The time-interleaved sampling system is extremely sensitive to the mismatches between the sub-ADCs. The signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are not as good as a system that is built up with a single ADC [7,8]. The mismatches include offset, gain and sample time skew; some papers analyze the mismatch effects in a time-interleaved system and introduce some compensation methods, divided into foreground and background calibrations [9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Synchronous Mixing Architecture for Digital Bandwidth Interleaving Sampling System

Jiang

2021

Electronics

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By using a mixer to down-convert the high frequency components of a signal, digital bandwidth interleaving (DBI) technology can simultaneously increase the sampling rate and bandwidth of the sampling system, compared to the time-interleaved and hybrid filter bank. However, the software and hardware of the classical architecture are too complicated, which also leads to poor performance. In particular, the pilot tone used to synchronize the analog and digital local oscillators (LO) of mixers intermodulates with the high frequency components of the signal, resulting in larger spurs. This paper proposes a synchronous mixing architecture for the DBI system, where the LO of the analog mixer is synchronized with the sampling clock of the analog-to-digital converter. Its hardware and software are simplified—the pilot tone used to synchronize the LOs can also be removed. An evaluation platform with a sampling rate of 250 MSPS is implemented to illustrate the performance of the new architecture. The result shows that the spurious free dynamic range (SFDR) of the new architecture is more than 20 dB higher than the classical one in a high frequency range. The rise time of a step signal of the new architecture is 0.578 ± 0.070 ns faster than the classical one with the same bandwidth (90 MHz).

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“…This solution improves the digital circuit deployed between the ADC and the acquisition memory such that it can digitally downsample the signal by a factor within the interval

. This is sufficient to grant fine sample rate choices in a wide range, since fine frequency resolution becomes also available to lower values using one decimation factor within the interval

followed by an additional integer decimation step [ 22 , 23 , 24 ]. Clearly, the need of real-time execution and fine sample rate selections, make the downsampling task much more challenging with respect to post-processing applications, where downsampling can be considered little more than an elementary task [ 25 , 26 , 27 , 28 , 29 ].…”

Section: Introductionmentioning

confidence: 99%

Enabling Fine Sample Rate Settings in DSOs with Time-Interleaved ADCs

D’Arco

Napoli

Zacharelos

et al. 2021

Sensors

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The time-base used by digital storage oscilloscopes allows limited selections of the sample rate, namely constrained to a few integer submultiples of the maximum sample rate. This limitation offers the advantage of simplifying the data transfer from the analog-to-digital converter to the acquisition memory, and of assuring stability performances, expressed in terms of absolute jitter, that are independent of the chosen sample rate. On the counterpart, it prevents an optimal usage of the memory resources of the oscilloscope and compels to post processing operations in several applications. A time-base that allows selecting the sample rate with very fine frequency resolution, in particular as a rational submultiple of the maximum rate, is proposed. The proposal addresses the oscilloscopes with time-interleaved converters, that require a dedicated and multifaceted approach with respect to architectures where a single monolithic converter is in charge of signal digitization. The proposed time-base allows selecting with fine frequency resolution sample rate values up to 200 GHz and beyond, still assuring jitter performances independent of the sample rate selection.

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Automatic Calibration Method of Channel Mismatches for Wideband TI-ADC System

Cited by 22 publications

References 32 publications

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

Synchronous Mixing Architecture for Digital Bandwidth Interleaving Sampling System

Enabling Fine Sample Rate Settings in DSOs with Time-Interleaved ADCs

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