Automatic creation of domain-specific reconfigurable CPLDS for SOC

Holland, M.; Hauck, Scott

doi:10.1109/fpl.2005.1515705

Cited by 3 publications

(6 citation statements)

References 4 publications

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“…Table 2 displays the area, delay, and area-delay product results obtained by using sparse-crossbar based CPLD architectures, compared to the results for full-crossbar based architectures from [1]. Our search algorithm found different PLA sizes for our new CPLD architectures, migrating to other effective architectures that were better able to leverage the use of sparse crossbars.…”

Section: Required Jog Pitches Domainmentioning

confidence: 99%

“…Specifically, by altering the sizes of our PLAs in terms of inputs, product terms, and outputs, and by reducing the connectivity of the interconnect structure, CPLD architectures can be created that perform better than "typical" CPLD architectures for a specified domain. This paper presents a method for creating sparse-crossbar based CPLD architectures, including a novel switch smoothing algorithm, which will provide improved performance over the full-crossbar based architectures we previously developed [1]. We also provide an analysis of the CPLD resources that should be added to an architecture in order to support future, unknown circuits that exist in the computational domain that we are targeting.…”

Section: Figure 1 a Cpld With Central Interconnectmentioning

confidence: 99%

“…PLAs are characterized by their input, product term, and output capacities, and the same PLA size is used for each occurrence in the CPLD. Several different algorithms were presented and evaluated in [1], and the best of those algorithms is used here. The PLA search space is 3-dimensional, as we must specify the number of inputs, product terms, and outputs for the PLA.…”

Section: Search Algorithmmentioning

confidence: 99%

“…We have also performed an analysis of the benefits that are achieved by using domain-specific full-crossbar based CPLDs instead of fixed CPLDs [1]. In this work we created an efficient algorithm for finding domain-specific CPLD architectures by determining an effective size for the PLAs in the architecture, and developed an automated layout process for creating full VLSI layouts of the architectures we specify.…”

Section: Introductionmentioning

confidence: 99%

“…When using sparse crossbars, there is no guarantee that a signal from the interconnect can reach any PLA input, so a router must be employed. In this paper we will discuss the important elements of the tool flow developed for creating full-crossbar based CPLDs [1], and present the algorithms necessary for creating sparse-crossbar based CPLD architectures. We will then address the question of how to add resources to our CPLDs in order to maximize the likelihood that future circuits are supported.…”

Section: Introductionmentioning

confidence: 99%

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Very large scale integration

1982

Microprocessing and Microprogramming

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Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurability, or even be used for post-fabrication modifications. Also, by tailoring the logic to the SoC domain, additional area and delay gains can be achieved over current, more general reconfigurable fabrics. This paper presents our work on creating efficient CPLD architectures for SoC, including the creation of sparse crossbars, and a novel switch smoothing algorithm which makes the crossbars amenable to layout. For our largest architecture, the switch smoothing algorithm reduced the layout's wire jog pitch from 48 to just 3, allowing for a compact VLSI layout. This has helped pave the way for our sparse-crossbar based CPLDs, which require just .37x the area and .30x the delay of our full-crossbar based CPLDs.However, regardless of how efficient an architecture we develop, it is useless if it does not have enough resources to support the circuits to be implemented. We also address the question of how best to add resources to a CPLD in order to support future, unknown circuits, concluding that the best strategy is to add 5% to the crossbar switch density and to provide additional PLAs of the same size found in the base architecture.

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Section: Required Jog Pitches Domainmentioning

confidence: 99%

Section: Figure 1 a Cpld With Central Interconnectmentioning

confidence: 99%

Section: Search Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Very large scale integration

1982

Microprocessing and Microprogramming

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A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm

Aken'Ova

Saleh

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

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Our recent work in embedded FPGAs has been focused on a soft IP approach where programmable fabrics are described at the RTL level and implemented using the ASIC digital flow and generic standard cells. Early results showed significant penalties in area, delay, and power overhead. However, using tactical standard cells and a structured physical design approach within such a flow, we were able to obtain large savings in area and delay. We defined this new approach as soft++ eFPGA. This paper provides details of the physical design flow, with particular emphasis on floor-planning, interconnect-planning, and clock tree synthesis. The advantages of our approach in handling larger circuits are demonstrated on a set of realistic benchmark circuits implemented in 180nm and 90nm CMOS process technology.

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Design space exploration for application specific FPGAS in system-on-a-chip designs

Hammerquist

Lysecky

2008

2008 IEEE International SOC Conference

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The inclusion of field programmable gate arrays (FPGAs) within a system-on-a-chip (SOC) design offers programmability, flexibility, and reconfigurability not possible with application specific integrated circuits (ASIC) or fullcustom implementations. However, these benefits come at the expense of significant area, performance, and power consumption overheads compared to ASIC or full-custom circuits. As a typical SOC design will require fabrication of the final integrated circuit, rather than rely on a generic FPGA architecture, an FPGA integrated within an SOC design can be optimized for the specific intended application. In this paper, we present an initial design space exploration framework for generating an application specific FPGA (ASFPGA) by tailoring several FPGA architectural features for a specific hardware circuit to improve the area, delay, or energy consumption compared to traditional FPGA designs and reduce the overheads of utilizing an FPGA compared to ASIC and full custom implementations.

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Automatic creation of domain-specific reconfigurable CPLDS for SOC

Cited by 3 publications

References 4 publications

Very large scale integration

Very large scale integration

A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm

Design space exploration for application specific FPGAS in system-on-a-chip designs

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