Automatic custom instruction identification in memory streaming algorithms

Haab, Martin; Bauer, Lars; Henkel, Jörg

doi:10.1145/2656106.2656114

Cited by 6 publications

(5 citation statements)

References 30 publications

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“…There are other efforts to profile the applications at different levels such as basic block level in static single assignment (SSA) form to find out the most frequently executed instruction sequences [72,73]. However, we maintained the analysis at a higher level of abstraction to keep it simple and architecture agnostic.…”

Section: Discussionmentioning

confidence: 99%

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

2018

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The last ten years have seen performance and power requirements pushing computer architectures using only a single core towards so-called manycore systems with hundreds of cores on a single chip. To further increase performance and energy efficiency, we are now seeing the development of heterogeneous architectures with specialized and accelerated cores. However, designing these heterogeneous systems is a challenging task due to their inherent complexity. We proposed an approach for designing domain-specific heterogeneous architectures based on instruction augmentation through the integration of hardware accelerators into simple cores. These hardware accelerators were determined based on their common use among applications within a certain domain.The objective was to generate heterogeneous architectures by integrating many of these accelerated cores and connecting them with a network-on-chip. The proposed approach aimed to ease the design of heterogeneous manycore architectures-and, consequently, exploration of the design space-by automating the design steps. To evaluate our approach, we enhanced our software tool chain with a tool that can generate accelerated cores from dataflow programs. This new tool chain was evaluated with the aid of two use cases: radar signal processing and mobile baseband processing. We could achieve an approximately 4× improvement in performance, while executing complete applications on the augmented cores with a small impact (2.5-13%) on area usage. The generated accelerators are competitive, achieving more than 90% of the performance of handwritten implementations.

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Section: Discussionmentioning

confidence: 99%

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

2018

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“…The results obtained can also be used to analyze applications in the design of ASIP (Application-Specific Integrated Processor). A similar algorithm for selecting user instructions for ASIP is developed in [ 25 , 26 ].…”

Section: Analysis Of Existing Review Workmentioning

confidence: 99%

Analytical Modeling for Identification of the Machine Code Architecture of Cyberphysical Devices in Smart Homes

Kotenko

Izrailov

Buinevich

2022

Sensors

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Ensuring the security of modern cyberphysical devices is the most important task of the modern world. The reason for this is that such devices can cause not only informational, but also physical damage. One of the approaches to solving the problem is the static analysis of the machine code of the firmware of such devices. The situation becomes more complicated in the case of a Smart Home, since its devices can have different processor architectures (means instruction sets). In the case of cyberphysical devices of the Smart Home, the destruction of machine code due to physical influences is also possible. Therefore, the first step is to correctly identify the processor architecture. In the interests of this, a machine code model is proposed that has a formal notation and takes into account the possibility of code destruction. The article describes the full cycle of research (including experiment) in order to obtain this model. The model is based on byte-frequency machine code signatures. The experiment resulted in obtaining template signatures for the Top-16 processor architectures: Alpha, X32, Amd64, Arm64, Hppa64, I486, I686, Ia64, Mips, Mips64, Ppc, Ppc64, RiscV64, S390, S390x and Sparc64.

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“…We count on the same data bandwidth as for other processor instructions using the processor's memory hierarchy. Despite the fact that there exist CIs with memory support [Haaß et al 2014], our CIs read and write data from and to the processor's register file to simplify the design and to not greatly increase power consumption beyond the processor's baseline. We also do not consider parallel execution of the DSFU with the processor's functional units because the performance improvement is not significant enough [Carrillo and Chow 2001].…”

Section: Target Architecture Modelmentioning

confidence: 99%

MInGLE

Gonzalez-Alvarez

Sartor

Álvarez

et al. 2016

ACM Trans. Archit. Code Optim.

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The end of Dennard scaling leads to new research directions that try to cope with the utilization wall in modern chips, such as the design of specialized architectures. Processor customization utilizes transistors more efficiently, optimizing not only for performance but also for power. However, hardware specialization for each application is costly and impractical due to time-to-market constraints. Domain-specific specialization is an alternative that can increase hardware reutilization across applications that share similar computations. This article explores the specialization of low-power processors with custom instructions (CIs) that run on a specialized functional unit. We are the first, to our knowledge, to design CIs for an application domain and across basic blocks, selecting CIs that maximize both performance and energy efficiency improvements. We present the Merged Instructions Generator for Large Efficiency (MInGLE), an automated framework that identifies and selects CIs. Our framework analyzes large sequences of code (across basic blocks) to maximize acceleration potential while also performing partial matching across applications to optimize for reuse of the specialized hardware. To do this, we convert the code into a new canonical representation, the Merging Diagram, which represents the code’s functionality instead of its structure. This is key to being able to find similarities across such large code sequences from different applications with different coding styles. Groups of potential CIs are clustered depending on their similarity score to effectively reduce the search space. Additionally, we create new CIs that cover not only whole-body loops but also fragments of the code to optimize hardware reutilization further. For a set of 11 applications from the media domain, our framework generates CIs that significantly improve the energy-delay product (EDP) and performance speedup. CIs with the highest utilization opportunities achieve an average EDP improvement of 3.8 × compared to a baseline processor modeled after an Intel Atom. We demonstrate that we can efficiently accelerate a domain with partially matched CIs, and that their design time, from identification to selection, stays within tractable bounds.

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Automatic custom instruction identification in memory streaming algorithms

Cited by 6 publications

References 30 publications

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

Analytical Modeling for Identification of the Machine Code Architecture of Cyberphysical Devices in Smart Homes

MInGLE

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