Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

Abstract

The last ten years have seen performance and power requirements pushing computer architectures using only a single core towards so-called manycore systems with hundreds of cores on a single chip. To further increase performance and energy efficiency, we are now seeing the development of heterogeneous architectures with specialized and accelerated cores. However, designing these heterogeneous systems is a challenging task due to their inherent complexity. We proposed an approach for designing domain-specific heterogeneous architectures based on instruction augmentation through the integration of hardware accelerators into simple cores. These hardware accelerators were determined based on their common use among applications within a certain domain.The objective was to generate heterogeneous architectures by integrating many of these accelerated cores and connecting them with a network-on-chip. The proposed approach aimed to ease the design of heterogeneous manycore architectures-and, consequently, exploration of the design space-by automating the design steps. To evaluate our approach, we enhanced our software tool chain with a tool that can generate accelerated cores from dataflow programs. This new tool chain was evaluated with the aid of two use cases: radar signal processing and mobile baseband processing. We could achieve an approximately 4× improvement in performance, while executing complete applications on the augmented cores with a small impact (2.5-13%) on area usage. The generated accelerators are competitive, achieving more than 90% of the performance of handwritten implementations.

Designing Application-Specific Heterogeneous Architectures from Performance Models

“…Suleyman et al [27] present a generic methodology for designing domain-specific heterogeneous many-core architectures based on accelerators integrated into simple cores, which is comparable to ours. They reveal the steps undertaken to integrate the accelerators into an open source core and use them via custom instructions.…”

Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators

“…Similarly, Savas et al [11], [12] proposed a framework to design a domain-specific heterogeneous many-core architecture from application data flow graphs. The framework is based on a heterogeneous tile-based architecture consisting of a simple RISC-V core, memory and accelerator tiles connected through a NoC.…”

“…Furthermore, in comparison with HERO [7] with similar RV32 extensions for PE, the hardware resources utilization of (LUTs and FFs) are less than ∼30% of HERO's cluster resources utilization while using 4 PEs (half of PEs number used by [7]). In contrast, the tile-based architectures of [8], [10], [12] support a single core RV64G/C with floating point execution unit and multiple levels of caches subsystems which increase the resources utilization compared to the proposed cluster-based architecture with scratchpad memories and less complex RISC-V cores.…”

Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit

“…We have used the square root hardware, that is implemented in this paper, in an accelerator utilized for accelerating QR decomposition. The accelerator uses single-precision floatingpoint numbers and it is integrated to a RISC-V [14] core to build a heterogeneous tile [15]. It performs the square root operation on single-precision floating-point numbers represented in IEEE-754 standard format.…”