Automatic datapath tile placement and routing

Serdar, T.; Sechen, Carl

doi:10.1109/date.2001.915078

Cited by 3 publications

(3 citation statements)

References 11 publications

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“…In [4], Ward et al discuss extracting data-paths using a novel data learning technique and a new placement algorithm. In [5], Serdar et al present a design flow for automatic data-path placement using simulated annealing and a global placement flow based on the o-tree algorithm. Liew et al in [6] proposed a manual placement algorithm for handling SDP elements using Integrated Circuit Compiler I (ICC I) from Synopsys.…”

Section: Related Workmentioning

confidence: 99%

“…However, these tools do not extract the SDP elements automatically and place them. Though there are many algorithms proposed to extract data-path elements automatically in [1][2][3][4][5][6], design knowledge is essential to extract the data-path structures and place them; therefore, none of the commercial tools have automatic data-path extraction in their flow. Therefore, extracting the SDP elements is an essential step in custom placement of them.…”

Section: Related Workmentioning

confidence: 99%

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Methodology for Structured Data-Path Implementation in VLSI Physical Design: A Case Study

et al. 2022

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State-of-the-art modern microprocessor and domain-specific accelerator designs are dominated by data-paths composed of regular structures, also known as bit-slices. Random logic placement and routing techniques may not result in an optimal layout for these data-path-dominated designs. As a result, implementation tools such as Cadence’s Innovus include a Structured Data-Path (SDP) feature that allows data-path placement to be completely customized by constraining the placement engine. A relative placement file is used to provide these constraints to the tool. However, the tool neither extracts nor automatically places the regular data-path structures. In other words, the relative placement file is not automatically generated. In this paper, we propose a semi-automated method for extracting bit-slices from the Innovus SDP flow. It has been demonstrated that the proposed method results in 17% less density or use for a pixel buffer design. At the same time, the other performance metrics are unchanged when compared to the traditional place and route flow.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Methodology for Structured Data-Path Implementation in VLSI Physical Design: A Case Study

et al. 2022

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“…Automatic placement of structured circuits has been performed by dedicated datapath placers such as [1], [7], [8], which generate highly compact, area efficient placements. After layout generation, these methods construct a larger macro block or small individual bit-slice macro blocks, followed by the main random-logic mixed-size placer.…”

Section: A Need For a Unified Placement Frameworkmentioning

confidence: 99%

Structure-Aware Placement Techniques for Designs With Datapaths

Kim

Viswanathan

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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As technology scales and frequencies increase, a new hybrid design style emerges, wherein designs contain a mixture of random logic and datapath standard-cell components. This paper demonstrates that conventional half-perimeter wirelength driven placers underperform in terms of regularity and Steiner wirelength (StWL) for such hybrid designs. In addition, the quality gap between manual and automatic placement is more pronounced as the designs become more datapath oriented. To effectively handle hybrid designs, this paper proposes a new unified placement flow that simultaneously places random logic and datapath cells. This flow is built on the top of a leading academic force-directed placer and significantly improves the quality of datapath placement while leveraging the speed and flexibility of existing random-logic placement algorithms. It consists of a suite of novel global and detailed placement techniques, collectively called structure-aware placement techniques (SAPT). These techniques effectively integrate alignment constraints into placement, thereby overcoming the deficiencies of existing randomlogic placers when handling designs with embedded datapaths. Compared to other state-of-the-art placers, SAPT improves total StWL by more than 28% and total routing overflow by over six times on the ISPD 2011 datapath benchmark suite. In addition, it improves total StWL by 5.8% on industrial hybrid designs.

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