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We present two major extensions to the implementation of simulated annealing for row-based placement which have enabled it to obtain the best results ever reported for a large set of MCNC benchmark circuits while using the least computation time ever reported for remotely comparable results. Our results indicate that chip area reductions up to 16% can be expected, compared with TimberWolfSC 16.0. Our new hierarchical annealing-based placement program yields total wire length reductions of up to 9% while consuming up to 7.5 times less CPU time in comparison to TimberWolflC v6.0. In comparison to the Gordiad Domino program [21[31[41, our new program yields total wire lengths which are always lower (up to 9% lower) and our program is always faster for circuits with more than 5000 cells (which represents the range of circuit sizes of interest).

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LIbrary of Congress Cataloglng•ln.Publicatlon Data Sechen, Carl, 1956-VLSI placement and global routing using simulated annealing/by Carl Sechen. p. cm.-(The Kluwer international series in engineering and computer science; 54) Bibliography: p. Includes index.