VLSI Placement and Global Routing Using Simulated Annealing

Sechen, Carl

doi:10.1007/978-1-4613-1697-8

Cited by 176 publications

(62 citation statements)

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“…force directed placement [4] or simulated annealing [13], [21]) as well. The running time of the underlying placement algorithm will hardly increase with our framework; the extra work we need is a (very fast) congestion estimation and a few additional repartitioning steps (as described later).…”

Section: Goalsmentioning

confidence: 99%

An effective congestion driven placement framework

Brenner

Rohe

2002

Proceedings of the 2002 International Symposium on Physical Design

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We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1,300,000 cells are presented: The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.

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Section: Goalsmentioning

confidence: 99%

An effective congestion driven placement framework

Brenner

Rohe

2002

Proceedings of the 2002 International Symposium on Physical Design

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“…The core of our approach is a timing driven simulated annealing-based standard cell placement algorithm following the philosophy of common placement tools such as [18]. Figure 9 gives an overview of the placement procedure at a particular temperature level.…”

Section: Overviewmentioning

confidence: 99%

Placement driven retiming with a coupled edge timing model

Neumann¹,

Kunz²

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

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Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the predicted performance improvement will still be valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model taking into account the effect of retiming on capacitive loads of single wires as well as fanout systems. We propose the integration of retiming into a timing-driven standard cell placement environment based on simulated annealing. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on standard FEAS our approach achieved an improvement in cycle time of up to 34% and 17% on the average.

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“…Since two-way min-cut partitioning is NP-complete [19], a number of approximate schemes have been proposed. These include iterative improvement methods [16], [17], [23], [24], [29], [30], simulated annealing [31], [32] and clustering-based techniques [5], [7], [18], [20], [28], [29], [35], [36]. An excellent survey on partitioning techniques appears in [6].…”

Section: Ery Large Scale Integration (Vlsi) Circuitmentioning

confidence: 99%

A probability-based approach to VLSI circuit partitioning

Dutt¹,

Deng²

33rd Design Automation Conference Proceedings, 1996

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Abstract-Iterative-improvement two-way min-cut partitioning is an important phase in most circuit placement tools, and finds use in many other computer-aided design (CAD) applications. Most iterative improvement techniques for circuit netlists like the Fiduccia-Mattheyses (FM) method compute the gains of nodes using local netlist information that is only concerned with the immediate improvement in the cutset. This can lead to misleading gain information. Krishnamurthy suggested a lookahead (LA) gain calculation method to ameliorate this situation; however, as we show, it leaves room for improvement. We present here a probabilistic gain computation approach called probabilistic partitioner (PROP) that is capable of capturing the future implications of moving a node at the current time. We also propose an extended algorithm SHRINK-PROP that increases the probability of removing recently "perturbed" nets (nets whose nodes have been moved for the first time) from the cutset. Experimental results on medium-to large-size ACM/SIGDA benchmark circuits show that PROP and SHRINK-PROP outperform previous iterative-improvement methods like FM (by about 30% and 37%, respectively) and LA (by about 27% and 34%, respectively). Both PROP and SHRINK-PROP also obtain much better cutsizes than many recent state-of-the-art partitioners like EIG1, WINDOW, MELO, PARABOLI, GFM and GMetis (by 4.5% to 67%). Our empirical timing results reveal that PROP is appreciably faster than most recent techniques. We also obtain results on the more recent ISPD-98 benchmark suite that show similar substantial mincut improvements by PROP and SHRINK-PROP over FM (24% and 31%, respectively). It is also noteworthy that SHRINK-PROP's results are within 2.5% of those obtained by hMetis, one of the best multilevel partitioners. However, the multilevel paradigm is orthogonal to SHRINK-PROP. Further, since it is a "flat" partitioner, it has advantages over hMetis in partition-driven placement applications.Index Terms-Clustering effect, iterative-improvement, min-cut partitioning, probabilistic gain, VLSI circuit.

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VLSI Placement and Global Routing Using Simulated Annealing

Abstract: LIbrary of Congress Cataloglng•ln.Publicatlon Data Sechen, Carl, 1956-VLSI placement and global routing using simulated annealing/by Carl Sechen. p. cm.-(The Kluwer international series in engineering and computer science; 54) Bibliography: p. Includes index.

Cited by 176 publications

References 0 publications

An effective congestion driven placement framework

An effective congestion driven placement framework

Placement driven retiming with a coupled edge timing model

A probability-based approach to VLSI circuit partitioning

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